Synopsys Synplify FPGA Synthesis tool
Synplify is a tool for synthesizing Verilog and VHDL hardware designs for programmable FPGA chips.
Questions tagged [synplify]
7 questions
3
votes
4 answers
Defining different parameter value for simulation and synthesis
I'm using systemVerilog and I have a package that holds some of my modules parameter values (for example parameter SPI_RATE = 2_000_000;). Is there any way I can set one value for simulation and a different one for synthesis? (I'm using…
MRm
- 517
- 2
- 14
0
votes
2 answers
Why is the wired or signal type (wor) disallowed for typedefs in SystemVerilog
In SystemVerilog I CAN do
typedef logic [15:0] bus16;
typedef reg [15:0] reg16;
interface myif;
bus16 mybus;
wor [15:0] myotherbus;
endinterface
But I CAN'T do
typedef wor [15:0] wor16;
interface myif;
wor16 myotherbus;
endinterface
I…
Jay M
- 3,736
- 1
- 24
- 33
0
votes
1 answer
VHDL, error message; has multiple drivers
Im creating an Alu, these is my code.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is port (
entrada: in std_logic_vector(11 downto 0);
S: in std_logic_vector(3 downto 0);
load : in std_logic;
…
Alessia Houston
- 9
- 4
0
votes
1 answer
Conditional use of libraries when simulating VHDL design with ModelSim in Pre-Synthesis / Post-Synthesis
In my VHDL design there is a 16-bits std_logic_vector. The bit in position 15 is currently not used and the synthesizer (SynplifyPro) throws a warning saying that bit is not used and will be pruned:
@W:CL190 : DATAGEN.vhd(93) | Optimizing register…
Alexis
- 576
- 1
- 10
- 29
0
votes
1 answer
Synthesis of two simulation identical designs - with and without second if in process for SET clk
I have got two identical (by means of simulation) flip flop process in verilog.
First is just a standard description of register with asynchronous reset (CLR) and clock (SET) with data in tied to 1:
always @(posedge SET, posedge CLR)
if (CLR)
Q…
J. Doe
- 59
- 8
0
votes
1 answer
Synopsys Synplify Pro synthesis failed when using "``"
When I try to use construction like this my synthesis was failed
`define defLOMIC 0 //For example
`define rd(LOMIC) `def``LOMIC
Late:
wire lod = `rd(LOMIC);
Error:
E CS231 Unknown macro def VDF_TOP.v (368) syntax.log (13) 09:14:32 Thu Dec 06…
Vlad
- 17
- 5
-2
votes
1 answer
How to use the command "+incdir+" in synplify script(.tcl) when one verilog file include another verilog file?
I insert a verilog file into another verilog file by using "`include "
And when I used the synplify script(*.tcl) to try to synthesize, one error occured:
invalid command name "+incdir+<...>"
It seems like I have to use the command "+incdir+"…
Xiuhua Yang
- 7
- 1
- 3