Wait for input state change to start process

Question

I'm programming a Coolrunner2 (XC2C64A) CPLD with the ISE Project Navigator software. For now, it should only act as a logical or gate (output = o_buzzer) between a pin from a PIC32 (input = i_pic) and a RPi CM3 (input = i_cm).

o_buzzer <= i_pic or i_cm;

The problem is that when the power supply gets connected, the pins of the PIC32 are configured as inputs so the CPLD sees it as high impedance (Z) and outputs a 1 untill the pins are configured. So I'm trying to let the CPLD wait untill i_pic isn't Z anymore.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity or_gate is
    Port ( i_pic : in  STD_LOGIC;
           i_cm : in  STD_LOGIC;
           o_buzzer : out  STD_LOGIC);
end or_gate;

architecture Behavioral of or_gate is

begin

    process_or : process(i_pic,i_cm)

    begin

        while (i_pic = 'Z') loop

        end loop;

        o_buzzer <= i_pic or i_cm;
    end process process_or;

end Behavioral;

This gives me a warning:

line 46: Loop body will iterate zero times.

And when implementing it doesn't work. Buzzer still beeps till the pins are initialized.

Using the while loop:

while (i_pic = 'Z') loop
    o_buzzer <= '0';
end loop;

Gives me:

Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more."

How can I let the process wait untill i_pic is logical low and not Z anymore?

score 1 · Accepted Answer · answered Sep 02 '19 at 14:58

1

You cannot test for 'Z' in synthesisable code. You can test for a '1' (or 'H') or for a '0' (or 'L'). You cannot test for a 'Z'. What hardware would do this? Some kind of analogue hardware, not some kind of digital hardware. That is why you cannot test for 'Z' in synthesisable code.

answered Sep 02 '19 at 14:58

Matthew Taylor

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Not to mention a while loop iterates in 0 time in VHDL in that process - hence should never be used for synthesisable code (its a software concept) – Tricky Sep 02 '19 at 15:13
Ok, I'm quite new to VHDL. So I can't do anything to let the `or_process` start a couple of 100ms later? – Swedgin Sep 02 '19 at 16:24
2

It doesnt work like that - this is hardware. How would you implement a circuit that waited for 100ms? VHDL is not like programming - you need to draw the hardware before you write the code. – Tricky Sep 02 '19 at 17:35
1

For line 46 see IEEE Std 1076-2008, 16.8.2.4.4 Metalogical values in relational expressions "If the VHDL source code includes an equality operator (=) for which one operand is a static metalogical value and for which the other operand is not a static value, a synthesis tool shall interpret the equality relation as equivalent to the BOOLEAN value FALSE." The while condition iteration scheme is historically not supported in synthesis (IEEE Std 1076.6-2004, RTL Synthesis, withdrawn, 8.8.9 Loop statement) although vendors do with caveats. The loop is limited by an iteration limit in synthesis. – Sep 02 '19 at 23:30
@Swedgin You can design a circuit that waits for 100ms - a counter. You need to do that. – Matthew Taylor Sep 03 '19 at 07:38
@MatthewTaylor yes, I understand it now. Thing is, there isn't a dedicated clock line so then I'd need another GPIO from the RPi or PIC32 and poll it for logic '0' to know that they are initialized before the CPLD can output the or-gate. – Swedgin Sep 03 '19 at 09:24
@Swedgin If you want to implement a delay in logic, you need a clock. – Matthew Taylor Sep 03 '19 at 10:08

Wait for input state change to start process

1 Answers1