Dump all values of input outputs of submodule in vhdl project

Question

I have build a cpu in vhdl. The cpu contains alu, ram, mux and other submodules. Now I want to dump all the values of inputs and outputs of submodules into csv or vcd files. I want to observe the changes for suppose 20 clock cycle. How can I do it in VHDL. I am using ModelSim for simulation.

Thanks in advance.

The printing facility is textio. So go to google and search on "using VHDL textio". You will find many resources — Jim Lewis, Jul 15 '21 at 22:34
I can store data using textio. But my problem is how can I get those data from submodules from top hierarchy? — Maruf Monem, Jul 18 '21 at 08:32

score 0 · Answer 1 · answered Jul 20 '21 at 14:46

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Open a List Window in modelsim. Add the signals you want to dump. Run the sim.
File -> Write List -> Tabular.

answered Jul 20 '21 at 14:46

iglam

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Dump all values of input outputs of submodule in vhdl project

1 Answers1