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I've started Verilog not too long ago and am stuck with some conditional statements in my ripple adder. I have a 6 bit ripple adder (that works) but I want to add an extra functionality. I have a 2 bit variable, called 'changer' that;

if changer == 00, then display input1
if changer == 01, then display input2
else display the summation result.

Here is what I have.

`timescale 1ns/10ps

module SixBitRippleAdder(
    input [5:0] x, //Input 1
    input [5:0] y, //Input 2
    input sel, //Add or subtract switch
    input [1:0] changer, //Condition switch
    output overflow,
    output [5:0] sum
    );

    reg [5:0] w;
    wire [5:0] c_out; //Used for carries

    //6 bit adder by adding instantiating 6 1 bit adders
    FullAdder bit1(.a(x[0]), .b(y[0] ^ sel), .s(sum[0]), .cin(sel), .cout(c_out[0]));
    FullAdder bit2(.a(x[1]), .b(y[1] ^ sel), .s(sum[1]), .cin(c_out[0]), .cout(c_out[1]));
    FullAdder bit3(.a(x[2]), .b(y[2] ^ sel), .s(sum[2]), .cin(c_out[1]), .cout(c_out[2]));
    FullAdder bit4(.a(x[3]), .b(y[3] ^ sel), .s(sum[3]), .cin(c_out[2]), .cout(c_out[3]));
    FullAdder bit5(.a(x[4]), .b(y[4] ^ sel), .s(sum[4]), .cin(c_out[3]), .cout(c_out[4]));
    FullAdder bit6(.a(x[5]), .b(y[5] ^ sel), .s(sum[5]), .cin(c_out[4]), .cout(c_out[5]));

    assign overflow = c_out[5] ^ c_out[4];

    //Issue is with these conditions
    always @*
        begin
            if(changer == 2'b00)
                w = x;
            else if(changer == 2'b01)
                w = y;
            else
                w = sum;
        end

    assign sum = w;

endmodule

I'm trying to synthesis this but am having errors with my always block. The error is "Multiple Driver Nets"

Thank you very much

E. Cheng
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    Your full adders drive `sum`. So does `assign sum = w;`. You need a different signal name for the intermediate signal from the full adders to the selector or a different name for the output. –  Feb 24 '19 at 19:23

1 Answers1

1

I guess that you just need a different variable which would be a result of the summation:

wire [5:0] sumTmp;

then

FullAdder bit1(.a(x[0]), .b(y[0] ^ sel), .s(sumTmp[0]), .cin(sel), .cout(c_out[0]));
                                            ^^^^^^^^^
    ...

and later:

always @*
    begin
        if(changer == 2'b00)
            w = x;
        else if(changer == 2'b01)
            w = y;
        else
            w = sumTmp;
    end

assign sum = w;
Serge
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  • Cool. That seems to work. Is there a way to determine what 'sum' is after I determine what 'w' should is? Just out of curiosity. – E. Cheng Feb 25 '19 at 10:05
  • @E.Cheng`sum` will be assigned the value of `w`, so they will have the same value. you can use any waveform viewer or use $display, $monitor, ... to examine the values. – Serge Feb 25 '19 at 11:55