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the temp variable is storing data out of its range. The range is used to store the maximum final value but it is holding the previous value and goes on incrementing. The functionality of for loop which is condition based is not satisfingenter image description here

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity counter is
    Port (clk,rst:in std_logic;
          o:out integer range 0 to 15
         );
end counter;


architecture Behavioral of counter is
signal temp2:integer range 1 to 15:=0;
begin
   process(clk) is
   begin
       if rising_edge(clk) then
           if rst='1' then
               temp2<=0;
           else
              for i in 1 to 15
              loop
                 temp2<=temp2+1;
            
               end loop;

           end if;    
       end if;
  end process;
  o<=temp2;

  end Behavioral;
sarath jaladi
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    The problem statement `satisfing` (satisfying) is not specific, provide a [mcve] (Reproducible). Vivado Simulator rangecheck should be enabled to comply with the VHDL standard, 0 is out of the value range for temp2 and should cause a simulation error. Instead `if rst='1' then temp2<=1;`. The loop statement has no effect and can be eliminated, there's only one projected output waveform for any simulation time and signal update is queued. Integer arithmetic operations aren't modulo. The statement within the else condition could be `if temp2 = 15 then temp2 <= 1; else temp2 <= temp2 + 1; end if;` – user16145658 Oct 04 '21 at 18:15

1 Answers1

0

Range puts a constraint on an object (here the signal temp2) that says it is illegal, and hence, fail if this object receives a value that is outside of the range.

Your code then must take the actions (such as mod) to make this so.

Since your code assigns the value 0, I am assuming that you need to update your declaration as follows:

signal temp : integer range 0 to 15 ; 
. . . 
temp2<= (temp2+1) mod 16;
Jim Lewis
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