I have been looking extensively into the operation of the CORDIC IP for use with Sin and Cos in VHDL.
According to page 24 of the CORDIC V6 documentation: https://www.xilinx.com/support/documentation/ip_documentation/cordic/v6_0/pg105-cordic.pdf#G6.297366 , the Sin and Cos functionality with the module should only require a PHASE_IN to provide data, and should return an X_OUT and a Y_OUT corresponding to the sin and cos of the PHASE_IN respectively. The generated IP diagram also shows an aclk, s_axis_cartesian_tvalid and s_axis_phase_tvalid input are required, and the module returns s_axis_phase_tready, m_axis_dout_tdata, and m_axis_dout_tvalid. Table 2-1 indicates that PHASE_IN is on the input s_axis_phase_tdata, and X_OUT and Y_OUT are on the channel m_axis_dout_tdata. I have followed the steps on page 35 of the designing with IP guide: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug896-vivado-ip.pdf to generate an instantiation file which I have used to create a simple test bed.
However when I test a Sin Cos CORDIC IP while providing a constant aclk, setting the tvalid to high and proving a tdata of 0, I get nothing back from the module, even after waiting for a very large number of clock cycles (10000). I appear to get back undefined (U) values for both the s_axis_phase_tready and the m_axis_dout_tvalid along with a constant 0 from the m_axis_dout_tvalid, which seems to indicate something is wrong with my core instantiation, but I believe I have followed everything the documentation has provided.
I will promptly provide any new information if requested, but ultimately I'm wondering if I'm doing something wrong to utilize this IP?
