How can i writing test bench for multiple module?

Question

I am new in this field, I don't know if they've been asked before. I'm writing code by creating separate modules to get used to big projects. I have no problems creating modules, but I don't know how to create a testbench.So I should write test bench according to main module. but the main module was created with reference to 3 separate modules. How should be testbench of the following code? Can you help me with this code?

//location of the main program

module circuit1_main(A,sel_m,Q);

input [2:0]A;
input sel_m;
output Q;
wire clk_m,reset_m,ud_m,load_m;

wire [2:0]A;
wire sel_m;
wire Q;

wire internal1;
wire internal2;
wire internal3;
wire internal4;

circuit1_counter cnt1(.clk(clk_m),.reset(reset_m),
                 .en(1'b1),.ud(ud_m),.load(load_m),
                      .d(A),.cnt(internal1));

assign internal2 = ~internal1;


circuit1_mux mux1(.a(internal1),.b(internal2),
                  .sel(sel_m),.out(internal3));


circuit1_shiftreg shiftreg1(.clk(clk_m),.reset(reset_m),
                            .sin(internal3),.sout(internal4));

assign Q = internal4;

endmodule

score 1 · Accepted Answer · answered Aug 10 '19 at 20:00

I have some bad new for you: You can't really write a test-bench for your 'circuit1_main' as it is rather broken.

Your module has a number of internal signals: clk_m,reset_m,ud_m,load_m; which should all come from outside. They should all be input ports which you must drive from your test bench.

I suspect, from the usage of the name 'main' that you are more comfortable with using C, C++ or other standard programming language. It is very important to realise that writing HDL is rather different. I therefore suggest you have a look around at some existing HDL code.
I know that the internet is full of HDL examples of FIFOs, UARTS, Counters etc., but that test benches are few and far between, Here is one which has code and the test benches that come with them.

I would also suggest you do not split your code into modules which are very, very small: Your circuit1_mux would be one line of code: assign out = sel ? a : b ;¹ Writing a module and connecting it up is ten times more work then using that single line of code and less confusing. Is out equal to a or to b when sel_m is high?

¹_{Substituting your port name could make it `assign internal3 = sel_m ? internal1 : internal2; which make immediately clear to anybody that sel_m selects the internal1 case.}

How can i writing test bench for multiple module?

1 Answers1