Functional Coverage for Verilog based TB

Question

I am currently developing a Verilog based Testbench model for a DUT, I have experience with System Verilog TB and Verification IPs and this is my first time developing a pure verilog TB.

I have completed the basic blocks for running the simulation and its working as expected. But I am stuck at implementing the Functional Coverage(which I want to do in Sample Monitor block).I have extracted the Functional Coverage from the specifications but how do I implement it in Verilog code ?

We have below(example code to show the syntax) support in System verilog for functional coverage,

covergroup example_group @ (posedge en);
  parity : coverpoint  par {
    bins even  = {0};
    bins odd   = {1};
  }
endgroup

Is there a way to implement functional coverage as bins,points and groups(in System verilog) to track overall functional coverage in verilog based code?

Edit : I understood that there is no alternative syntax for coverage in verilog and I don't want to complicate and spend more time by implementing coverage counters. Also I can't convert my verilog TB to System Verilog due to some internal agreement issues.

No. Verilog is a much simpler language. SystemVerilog is a superset of Verilog. — Matthew Taylor, Jul 13 '20 at 07:36
bins are uses to count certain events. So, potentially you can program verilog to do a similar task. But in general it might take a lot of effort and code around it (your example is an easy one though, you just need two counters). In addition, there are coverage reporting tools for system verilog. You will need to figure out how to create reports in verilog as well. — Serge, Jul 13 '20 at 15:01

dave_59 · Accepted Answer · 2020-07-14T14:10:12.893

0

Yes, the covergroup is equivalent to this Verilog code

always @(posedge en) begin : example_group
                       integer even=0;
                       integer odd=0;
                       if (par == 0) even = even + 1;
                       if (par == 1) odd = odd + 1;
                     end

But the real time consuming part is writing the code that collects all these counters, merges the data from different tests, and generates the reports. Seems silly to re-invent this. Most tools give you this capability in SystemVerilog.

edited Jul 14 '20 at 14:10

answered Jul 13 '20 at 20:52

dave_59

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Both 'even' and 'odd' must be initialized to 0. The above code uses system verilog semantics. Both declarations must be moved to the module scope if it is just 'verilog'. – Serge Jul 14 '20 at 14:00
Picky! This code is Verilog-2001 compliant. But I don’t expect anyone to ever write it. – dave_59 Jul 14 '20 at 14:12
my bet :-)! i was talking about v95. However, inline initialization does not seem to work with v2k. But you are correct, there is no good reason to write it at all. – Serge Jul 14 '20 at 15:51

Functional Coverage for Verilog based TB

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