Syntax error near "in" of VHDL testbench in ISE14.7

Question

I am writing a testbench to simulate the component top_tb, but it displays a following syntax error.

XX/selfloop_in_chip_tb.vhd" Line 47: Syntax error near "in". ERROR:ProjectMgmt - 1 error(s) found while parsing design hierarchy.

I have checked the code for several times, but I still fail to debug it. Could anyone spare time to give me some help? Thank you a lot.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;


ENTITY selfloop_in_chip_tb IS
END selfloop_in_chip_tb;

architecture behavior of selfloop_in_chip_tb is 

  -- Component Declaration
    component top_tb 
    port(
            clkIn     : in  std_logic;
            AD_in_C1  : in  std_logic_vector(AD_BITS_NUM-1 downto 0);
            AD_in_S1  : in  std_logic_vector(AD_BITS_NUM-1 downto 0);
            AD_in_C2  : in  std_logic_vector(AD_BITS_NUM-1 downto 0);
            AD_in_S2  : in  std_logic_vector(AD_BITS_NUM-1 downto 0);
            DA_out_I1 : out std_logic_vector(DA_BITS_NUM-1 downto 0);
            DA_out_Q1 : out std_logic_vector(DA_BITS_NUM-1 downto 0);
            DA_out_I2 : out std_logic_vector(DA_BITS_NUM-1 downto 0);
            DA_out_Q2 : out std_logic_vector(DA_BITS_NUM-1 downto 0);
     

                 src_data_select : in std_logic;     
                 src_data_fromTop : in std_logic;     
                 enc_start_fromTop : in std_logic;    
                 send_en           : out std_logic;   
                 
                 
                 --发端
                 send_frames    : out std_logic_vector(23 downto 0);
                 --收端
                 recv_frames    : out std_logic_vector(23 downto 0);
                 err_frames     : out std_logic_vector(23 downto 0);
                 ldpc_out_start : out std_logic;
                 ldpc_out_ena   : out std_logic;
                 ldpc_out_data  : out std_logic
        );
    end component;
    
    --Inputs  
 
                 -- 信源选择信号
Line 47   signal      clkIn           : in std_logic   := '0';    
    signal      src_data_select : in std_logic   := '0';     
    signal      src_data_fromTop : in std_logic  := '0';   
    signal      enc_start_fromTop : in std_logic := '0';  

    signal        AD_in_C1  : in  std_logic_vector(AD_BITS_NUM-1 downto 0) := (others => '0');
    signal        AD_in_S1  : in  std_logic_vector(AD_BITS_NUM-1 downto 0) := (others => '0');
    signal        AD_in_C2  : in  std_logic_vector(AD_BITS_NUM-1 downto 0) := (others => '0');
    signal        AD_in_S2  : in  std_logic_vector(AD_BITS_NUM-1 downto 0) := (others => '0');  

    --Outputs   
                --观测信号
                    --发端
    signal      send_frames    : out std_logic_vector(23 downto 0);
    
                    --收端
    signal      recv_frames    : out std_logic_vector(23 downto 0);
    signal      err_frames     : out std_logic_vector(23 downto 0);
    signal      ldpc_out_start : out std_logic;
    signal      ldpc_out_ena   : out std_logic;
    signal      ldpc_out_data  : out std_logic;
 
    signal      send_en           : out std_logic;   
    signal        DA_out_I1 : out std_logic_vector(DA_BITS_NUM-1 downto 0);
    signal        DA_out_Q1 : out std_logic_vector(DA_BITS_NUM-1 downto 0);
    signal        DA_out_I2 : out std_logic_vector(DA_BITS_NUM-1 downto 0);
    signal        DA_out_Q2 : out std_logic_vector(DA_BITS_NUM-1 downto 0);  
      
   -- Clock period definitions
   constant clkIn_period : time := 7.8125 ns;  --128MHz时钟         

BEGIN
  -- Component Instantiation
          uut: top_tb PORT MAP(       
                  clkIn => clkIn,
                  AD_in_C1 => AD_in_C1,
                  AD_in_C2 => AD_in_C2,
                  AD_in_S1 => AD_in_S1,
                  AD_in_S2 => AD_in_S2,
                  
                  DA_out_I1 => DA_out_I1,
                  DA_out_I2 => DA_out_I2,
                  DA_out_Q1 => DA_out_Q1,
                  DA_out_Q2 => DA_out_Q2,   

                  src_data_select  => src_data_select,
                  src_data_fromTop => src_data_fromTop,
                  enc_start_fromTop => enc_start_fromTop,
                

                send_frames    => send_frames,
                    --收端
                recv_frames    => recv_frames,
                err_frames     => err_frames,
                ldpc_out_start => ldpc_out_start,
                ldpc_out_ena   => ldpc_out_ena,
                ldpc_out_data  => ldpc_out_data,
                
                send_en        => send_en
          );


   clkIn_process :process
   begin
        clkIn <= '0';
        wait for clkIn_period/2;
        clkIn <= '1';
        wait for clkIn_period/2;
   end process;
    
END;

fgagnaire · Answer 1 · 2020-07-21T02:27:08.087

The signals from line 47 can't be declare either as in or as out. I am guessing this is a bad copy past. simply remove the in/ out of those it will be fine.

here is my fixed file:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;


ENTITY selfloop_in_chip_tb IS
END selfloop_in_chip_tb;

architecture behavior of selfloop_in_chip_tb is 
    -- I had to add those 2 line to compile
    constant AD_BITS_NUM : integer := 8; 
    constant DA_BITS_NUM : integer := 8;
    
  -- Component Declaration
    component top_tb 
    port(
            clkIn     : in  std_logic;
            AD_in_C1  : in  std_logic_vector(AD_BITS_NUM-1 downto 0);
            AD_in_S1  : in  std_logic_vector(AD_BITS_NUM-1 downto 0);
            AD_in_C2  : in  std_logic_vector(AD_BITS_NUM-1 downto 0);
            AD_in_S2  : in  std_logic_vector(AD_BITS_NUM-1 downto 0);
            DA_out_I1 : out std_logic_vector(DA_BITS_NUM-1 downto 0);
            DA_out_Q1 : out std_logic_vector(DA_BITS_NUM-1 downto 0);
            DA_out_I2 : out std_logic_vector(DA_BITS_NUM-1 downto 0);
            DA_out_Q2 : out std_logic_vector(DA_BITS_NUM-1 downto 0);
     

                 src_data_select : in std_logic;     
                 src_data_fromTop : in std_logic;     
                 enc_start_fromTop : in std_logic;    
                 send_en           : out std_logic;   
                 
                 
                 --发端
                 send_frames    : out std_logic_vector(23 downto 0);
                 --收端
                 recv_frames    : out std_logic_vector(23 downto 0);
                 err_frames     : out std_logic_vector(23 downto 0);
                 ldpc_out_start : out std_logic;
                 ldpc_out_ena   : out std_logic;
                 ldpc_out_data  : out std_logic
        );
    end component;
    
    
    --Inputs  
 
                 -- 信源选择信号
    signal      clkIn           : std_logic   := '0';    
    signal      src_data_select : std_logic   := '0';     
    signal      src_data_fromTop : std_logic  := '0';   
    signal      enc_start_fromTop : std_logic := '0';  

    signal        AD_in_C1  :  std_logic_vector(AD_BITS_NUM-1 downto 0) := (others => '0');
    signal        AD_in_S1  :  std_logic_vector(AD_BITS_NUM-1 downto 0) := (others => '0');
    signal        AD_in_C2  :  std_logic_vector(AD_BITS_NUM-1 downto 0) := (others => '0');
    signal        AD_in_S2  :  std_logic_vector(AD_BITS_NUM-1 downto 0) := (others => '0');  

    --Outputs   
                --观测信号
                    --发端
    signal      send_frames    : std_logic_vector(23 downto 0);
    
                    --收端
    signal      recv_frames    :  std_logic_vector(23 downto 0);
    signal      err_frames     :  std_logic_vector(23 downto 0);
    signal      ldpc_out_start :  std_logic;
    signal      ldpc_out_ena   :  std_logic;
    signal      ldpc_out_data  :  std_logic;
 
    signal      send_en           :  std_logic;   
    signal        DA_out_I1 :  std_logic_vector(DA_BITS_NUM-1 downto 0);
    signal        DA_out_Q1 :  std_logic_vector(DA_BITS_NUM-1 downto 0);
    signal        DA_out_I2 :  std_logic_vector(DA_BITS_NUM-1 downto 0);
    signal        DA_out_Q2 :  std_logic_vector(DA_BITS_NUM-1 downto 0);  
      
   -- Clock period definitions
   constant clkIn_period : time := 7.8125 ns;  --128MHz时钟         

BEGIN
  -- Component Instantiation
          uut: top_tb PORT MAP(       
                  clkIn => clkIn,
                  AD_in_C1 => AD_in_C1,
                  AD_in_C2 => AD_in_C2,
                  AD_in_S1 => AD_in_S1,
                  AD_in_S2 => AD_in_S2,
                  
                  DA_out_I1 => DA_out_I1,
                  DA_out_I2 => DA_out_I2,
                  DA_out_Q1 => DA_out_Q1,
                  DA_out_Q2 => DA_out_Q2,   

                  src_data_select  => src_data_select,
                  src_data_fromTop => src_data_fromTop,
                  enc_start_fromTop => enc_start_fromTop,
                

                send_frames    => send_frames,
                    --收端
                recv_frames    => recv_frames,
                err_frames     => err_frames,
                ldpc_out_start => ldpc_out_start,
                ldpc_out_ena   => ldpc_out_ena,
                ldpc_out_data  => ldpc_out_data,
                
                send_en        => send_en
          );


   clkIn_process :process
   begin
        clkIn <= '0';
        wait for clkIn_period/2;
        clkIn <= '1';
        wait for clkIn_period/2;
   end process;
    
END;

ah,.. I made a silly mistake of grammar of testbench. The signal should not be defined "in" or "out" in architecture. Thank you a lot. — tranquil, Jul 21 '20 at 05:13
don't forget to accept answer when they are correct. The good functioning of the website depends on it. — fgagnaire, Jul 21 '20 at 13:24

Syntax error near "in" of VHDL testbench in ISE14.7

1 Answers1