System Verilog - Reading a line from testbench and splitting the data

Question

I'm a beginner in SystemVerilog Programming. I have a file called "input.in" and it has around 32 bits of data. The value is present in only one line of the file. The data once sent from the testbench must be split into an array or 4 variables, each containing only 8 bits of the input. Please. Somebody help me :(

Answer 1

I think, you want to split the 32 bits of data into 4 bytes of data. Please try the following:

{>>{a,b,c,d}} = var_32_bit ; //a,b,c,d are 8 bits variable. // var_32_bit is an array of 32 bits size or a 32-bit variable. {bit a[] or bit [31:0]}

Is this the one you need ?