I'm new to verilog, Is there a difference between writing a test bench for a pipelined module and writing a test bench for an ordinary module? I just need a simple example clarifying the expected difference in the test bench code for testing a pipelined module and a non pipelined module please. Note that the module that I'm testing is pipelined not the testbench.
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The main purpose of any test bench is to verify that your model is working correctly. So, usually the testbench generates inputs to the model and verifies outputs. For that reason it has to be written in such a way that it knows how the outputs should look like in a much more abstract way then the model under test. So, if you verify a pipe line, than the testbench should probably also contain an abstract queue which will move testbench data so that it could be compared with the model outputs. – Serge Feb 22 '18 at 03:16
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If you only want to verify the behaviour of the pipelined module as a whole, you could just build a simple UVM-based testbench architecture, like the example in the link: Simple UVM Testbench Example.
If you want to verify the connections between the internal components of the pipeline structure, you could build a Universal Verification Component (UVC) for each pipeline stage and a UVM verification environment that will include all UVCs.
In any way, if you want to verify the pipelined module as a black box, knowing only the expected responses from the desired inputs, it is about the same as verifying it as a non-pipelined module.
nick_g
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