Can I call a VHDL function inside Verilog

Question

I am currently trying to use certain legacy VHDL codes into my Verilog design. While it is possible to instantiate VHDL modules within Verilog, I could not find a way to call VHDL functions within Verilog. (Apart from wrapping it around in a VHDL module and instantiating the module). Is there anyway to directly call VHDL functions within Verilog?

Answer 1

It probably depends on the simulator. In Modelsim PE v10.2c for example, directly calling VHDL functions from a Verilog/SystemVerilog is not supported

Hierarchical References to a VHDL Object from a Verilog/SystemVerilog Scope

Supported Objects

The only VHDL object types that can be referenced are: signals, shared variables, constants, and generics not declared within processes. VHDL functions, procedures, and types are not supported, and you cannot read VHDL process variables

Modelsim PE User's Manual v10.2c, p.297

You can use a common package between SystemVerilog / VHDL modules with an import keyword, but again VHDL functions are not supported.

You better refer to your simulator's manual to see if it is supported or not, because apparently there's no universally accepted way to do it.

Answer 2

As @Ivoudour noted, The support for this feature is depended on simulator. However, for those that do, the usage should be largely the same. This means that you can simply treat a VHDL based component as just another module. This assumes that you compile the design to the same library.

The below example uses ModelSim Altera Edition v10.4b with the following structure: and_tb (VHDL) -> and_bits (verilog) -> and2 (VHDL)

and2.vhd

library ieee ;
use ieee.std_logic_1164.all ;

entity and2 is
    port (
        a   : in    std_logic;
        b   : in    std_logic;
        c   : out   std_logic
    );
end and2;

architecture behavior of and2 is
begin
    c <= a and b;
end behavior ;

and_bits.v

`default_nettype none
`timescale       1ns/1ns

module and_bits #(
    parameter W                     = 5           
) (   
    input wire  [W-1:0]  a,
    input wire  [W-1:0]  b,
    output wire [W-1:0]  c
);
    genvar i;
    for (i=0; i<=W-1; i=i+1) begin: AND_GENERATE
        and2 u_and2 (            
            .a (a[i]),
            .b (b[i]),
            .c (c[i])
        );
    end

endmodule

`resetall

and_tb.vhd

library ieee ;
use ieee.std_logic_1164.all ;

entity and_tb is
end and_tb;

architecture tb of and_tb is
    signal a : std_logic_vector(3 downto 0) := "0110";
    signal b : std_logic_vector(3 downto 0) := "1111";
    signal c : std_logic_vector(3 downto 0);


    component and_bits
        generic ( W : integer );
        port (
            a : in  std_logic_vector(W-1 downto 0);
            b : in  std_logic_vector(W-1 downto 0);
            c : out std_logic_vector(W-1 downto 0)
        );
    end component;

begin
    dut: and_bits
    generic map (W => 4)
    PORT MAP(a=>a, b=>b, c=>c);
end tb ;

Simulation

Type the following in ModelSim console

vlib work
vcom and2.vhd
vlog and_bits.v
vcom and_tb.vhd

and simulate as normal.