Questions tagged [system-verilog]

SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.

SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs - asic) and to develop tests and environments to validate these circuit descriptions.

It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.

3298 questions

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What is the difference between single (&) and double (&&) ampersand binary operators?

In IEEE 1800-2005 or later, what is the difference between & and && binary operators? Are they equivalent? I noticed that these coverpoint definitions behave identically where a and b are of type bit: cp: coverpoint a & b; cp: coverpoint a && b;

verilog system-verilog

asked Jun 26 '13 at 18:23

Victor Lyuboslavsky

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4 answers

How do I read an environment variable in Verilog/System Verilog?

How do I read an environment variable in Verilog ? (Running on a VCS simulator) I am trying to accomplish File=$fopen("$PATH/FileName","r"); $PATH is an environment variable.

environment-variables verilog system-verilog

asked Feb 22 '13 at 22:08

Jean

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2 answers

What is the meaning of the hex value syntax with an underscore? eg:parameter FOO = 20'h0002_0

Pretty much just the title. What does that underscore mean? How is this different from: parameter FOO = 20'h00020; I don't know what to look for to find an answer to this question as I don't know what this type of syntax is called.

parameters syntax verilog system-verilog

asked Sep 11 '12 at 20:40

supernun

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1 answer

Specifying variable range in Verilog using for loop

I am trying to write this code: for (i = 0; i <= CONST - 1'b1; i = i + 1'b1) begin : loop_inst if (i < 3) begin if (changed[i] & !done_q[i]) …

hardware verilog system-verilog

asked Jul 27 '11 at 16:14

typon

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2 answers

Detect timescale in System Verilog

How do I detect the timescale precision used in a simulation from the source code ?. Consider I have a configuration parameter(cfg_delay_i) of some delay value given by user in timeunits as fs .If the user gives 1000 , my code has to wait 1000fs or…

system-verilog modelsim uvm system-verilog-dpi

asked Oct 01 '19 at 04:42

Sreejin TJ

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2 answers

case statement with multiple cases doing same operation

I need to use a case statement with the control signal being 4 bits. I have multiple cases of those 4 bits doing the same operation, how do I make the code more concise? For ex: casez (fbe) //fbe is defined as logic [3:0] fbe; 4'b0000: begin …

verilog system-verilog

asked Dec 07 '17 at 19:15

Gaurav Gupte

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4 answers

Arrays of interface instances in SystemVerilog with parametrized number of elements

I'm using SystemVerilog for synthesis. I fought with the fact that arrays of interfaces are not really arrays in SystemVerilog and the index has to be a constant value, but got over it using at lot of boilerplate generate for and assign statements…

arrays interface verilog system-verilog

asked Jul 12 '17 at 13:16

apriori

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2 answers

Printing packed structs in System Verilog

I have a packed struct defined as shown below typedef struct packed { logic bit1; logic [7:0] byte1; } MyPackedStruct; MyPackedStruct myPackedStruct; Is there any SV built in function that I could use to print the structures similar to…

printing struct verilog system-verilog packed

asked Jul 02 '14 at 09:08

Vissu

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5 answers

Prevent systemverilog compilation if certain macro isn't set

I am writing a systemverilog module and I need to make sure that a certain macro is set to allow compilation to proceed. I have tried the below, but it simply gives the syntax error "unexpected SYSTEM_IDENTIFIER" $fatal. I know that does technically…

macros compilation verilog system-verilog hdl

asked Apr 24 '14 at 14:36

miles.sherman

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3 answers

Verilog ** Notation

What does ** mean in verilog? I have the following logic provided for a testbench localparam NUM_INPUT_BITS = 1; localparam NUM_OUTPUT_BITS = NUM_INPUT_BITS + 1; localparam MAX_OUTPUT_BIT = NUM_OUTPUT_BITS - 1; localparam…

verilog system-verilog

asked Jan 23 '14 at 14:54

Nathan Tornquist

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3 answers

Does SystemVerilog support downcasting?

Does SystemVerilog support downcasting (casting a base object to a derived object)? If so, how? The following downcast example does not work: class base; int a = 5; endclass class extend extends base; int b = 1; endclass module test; …

casting system-verilog

asked Dec 12 '13 at 16:12

Victor Lyuboslavsky

9,882
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87
134

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2 answers

SystemVerilog program block vs. traditional testbench

Are there any features of SV that a program block offers that can't be duplicated with other methods? The less concrete version of this question is: should I bother with program blocks for verification? I'm moving from an environment where we were…

unit-testing testing verilog system-verilog

asked Aug 23 '13 at 15:03

dan

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40

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2 answers

SystemVerilog: Passing interfaces to functions/tasks (for synthesis!)

Is there any synthesizable way to pass an interface to a function or a task? My use case is the following: I have a package with several functions (though I could convert them to tasks, if that helps :) ), all of which might be used in a module and…

interface system-verilog synthesis

asked Jan 21 '13 at 13:20

rainer

6,769
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1 answer

Arithmetic shift acts as a logical shift, regardless of the signed variable

I've got a register declared as so: logic signed [15:0][2:0][15:0] registers; When I place a 2's compliment number into the array and arithmetically shift the number, it logical shifts instead: registers[0][0] =…

verilog bit-shift system-verilog

asked Jan 07 '13 at 13:37

user1567095

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2 answers

Is there something like LINE in Verilog?

I am new to Verilog but have been a C programmer for years which makes me dangerous. I'm doing some Verilog for a class. I'd like to use C assert() style testing in my simulation code. https://en.wikipedia.org/wiki/Assert.h We aren't using System…

verilog system-verilog

asked Oct 13 '12 at 18:32

David Poole

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