What is the point of a "plain" begin-end block?

Question

I'm reading some third party Verilog, and found this:

function [31:0] factorial;
    input [3:0] operand;
    reg [3:0] index;

    begin
        factorial = operand ? 1 : 0;
        for(index = 2; index <= operand; index = index + 1)
        factorial = index * factorial;
    end
endfunction

It seems that the begin and end keywords are redundant here. Are they? What is their use?

Answer 1

I don't know about the general case, but in this specific case:

If a function contains more than one statement, the statements must be enclosed in a begin-end or fork-join block.

Source: Verilog Golden Reference Guide

Answer 2

Both answers are correct. If the Verilog task or function had multiple statements, they were also required to have begin-end statements. Starting in SystemVerilog-2005, we removed the requirement to put begin-end inside of something that already had a begin-end. Most of us on the committee thought it was silly to require a begin-end inside of something that was already going to have endfunction/endtask. I mean, come-on! Don't you think a compiler could figure out that when it got the endtask/endfunction statement that it was at the end of the task or function?? Removing the begin-end from tasks and functions cuts out a surprising amount of useless code. Score another point for SystemVerilog!

Answer 3

According to the SystemVerilog extension (IEEE Standard 1800-2009), begin/end are optional inside a function. However, your toolset (simulator, etc.) must be capable of understanding this syntax, which was introduced in 2005.