Assign ASCII character to wire in Verilog

Question

I understand that you can declare a string in a Verilog test bench as follows:

reg [8*14:1] string_value;  

initial 
    string_value = "Hello, World!";

I can then do things with this string, like use $display in a test bench to display it.

I haven't been successful in doing the same in a module when I flash it to my FPGA:

reg [8*14:1] string_value;  

always @(reset) 
begin
    string_value = "Hello, World!";
    // Do stuff with string value

Even assigning a single value does not work:

reg [8:1] char_value;  

always @(reset) 
begin
    char_value = "A";
    if (char_value == 8'h41)
        // Do stuff!

I want to shift the individual characters on an 8-bit bus to an LCD screen for display.

How can I work with strings in Verilog?

@Adam12 - Yes, I'm trying to print text on an LCD screen connected to my FPGA development board. Since this wasn't clear to both you and toolic, I'll edit the question to be more specific: I want to assign these 8-bit character values to an output of my module through a shift register. — Kevin Vermeer, Jan 29 '12 at 02:56
What exactly does not work? Do you get a synthesis error, or is the text simply not shown on the LCD? — mkrieger1, Feb 10 '17 at 14:58

score 9 · Answer 1 · answered Sep 13 '12 at 09:11

9

You can assign a string to a register type. Anyone who says otherwise is wrong. You might want to make your registers 0' based for it to work properly. I've done this in real FPGAs and it works.

answered Sep 13 '12 at 09:11

Stephen

819
8
8

8

To be clear. The verilog compiler will translate "A" to 8'h41, "AB" to 16'h4142, "ABC" to 24'h434241. Do not make it more complicated on yourselves by trying to think that the FPGA has to "support" this some how. All that happens is the compiler converts it from a nice human readable format into a number. – Stephen Sep 13 '12 at 11:01
1

Yes string values are just constants. Although synthesis tool may or may not allow registers to have non-zero initialisation/reset values depending on the technology used. Recent X/A tools have no problem initialising shift registers from constants straight out of reset/programming. – shuckc Jul 02 '13 at 16:38

score 7 · Answer 2 · answered Oct 19 '14 at 23:14

Define an array of bytes, then assign ASCII to each array element:

wire [7:0] foo [0:11];
assign foo[0]  = "H";
assign foo[1]  = "e";
assign foo[2]  = "l";
assign foo[3]  = "l";
assign foo[4]  = "o";
assign foo[5]  = " ";
assign foo[6]  = "W";
assign foo[7]  = "o";
assign foo[8]  = "r";
assign foo[9]  = "l";
assign foo[10] = "d";
assign foo[11] = "!";

You now have a constant with ASCII values in it that you can index into.

reg [7:0] data_out;
reg       data_out_valid;
reg [3:0] some_index;
:
// pushing data onto a bus
data_out       <= foo[some_index];
data_out_valid <= 1'd1;
some_index     <= some_index + 4'd1;

With appropriate index checking and control that should work.

score 3 · Answer 3 · answered Jun 24 '13 at 20:33

3

This works for me:

    reg [8*16:1] line1data = "Hello, World!   ";

Both in simulation and on a Spartan-3E FPGA

answered Jun 24 '13 at 20:33

Rafi

31
1

Just tested on ISE (Virtex-6), works like a charm. – Rodrigo Strauss Dec 17 '20 at 20:37

score 0 · Answer 4 · edited Apr 12 '14 at 22:35

0

output [8*14:1]string_value1;  
reg [8*14:1]string_value1;

always @ (posedge BIWEn)

if (BIWEn==1'b1 ||BIREn==1'b1)
    begin:START_STATE_WRITE
        psW=idleW;  //psW is Present State Write
        string_value1= "IDLE";
    end

![test bench] (c:\pictures)

edited Apr 12 '14 at 22:35

Anshul Goyal

73,278
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186

answered Apr 12 '14 at 22:07

jay

1

toolic · Answer 5 · 2023-05-28T10:12:03.557

0

Here is a demonstration of how strings work in a module:

module tb;

reg [8:1] char_value;

initial begin
    char_value = "A";
    $display("%h", char_value);
    if (char_value == 8'h41) begin
        $display("match");
    end else begin
        $display("no match");
    end
end

endmodule

Prints out:

41
match

The string data type was introduced into the SystemVerilog standard in 2005 (refer to IEEE 1800-2005 or 1800-2009).

edited May 28 '23 at 10:12

answered Jan 27 '12 at 13:44

toolic

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I'm trying to assign the ASCII value to an 8-bit bus; I don't have `$display`. – Kevin Vermeer Jan 27 '12 at 22:27
For simulation, you can use string or $display. But if you are designing some code for FPGA. I think currently the synthesis tool doesn't support string type. From Xilinx they even doesn't support systemverilog now. – Enze Chi Feb 08 '12 at 10:07

Enze Chi · Accepted Answer · 2018-03-22T05:09:38.327

-3

SystemVerilog should support string assignment as mentioned in spec:

For example, to store the 12-character string "Hello world\n" requires a variable 8x12, or 96 bits wide. 
     bit [8*12:1] stringvar = "Hello world\n";

Not sure if the old verilog supports it or not.

edited Mar 22 '18 at 05:09

answered Feb 07 '12 at 11:07

Enze Chi

1,733
17
28

1

This answer is completely and utterly incorrect. Verilog does support character constants, and there is certainly nothing preventing a user from assigning hexadecimal values to registers! – Mar 19 '18 at 01:52

Assign ASCII character to wire in Verilog

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