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Questions tagged [synthesis]

Synthesis turns a high level circuit description into an implementation in logic gates.

Synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL) described in VHDL or Verilog, is turned into a design implementation in terms of logic gates.

Wikipedia

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Verilog Is this synthesizable read from array

Is the following code synthesizable? reg [15:0] litlen_buff0[3:0]; reg [1:0] rcount0; assign litlen_buff0_out = litlen_buff0[rcount0];
Janbert Jadraque
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I want to check for 'XX' in memory array using synthesizable verilog

I have a memory array which consists of series of valid values, starting from location 0. Rest of the values are 'XX'. I want to count the number of valid values in the memory. One way I can think of is by looking out for 'XX' for the first time…
Anurag Goyal
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Multiple objects in a loop C++ without "new" keyword

I have a scenario where I need to create different objects in each iteration of a 'for' loop. The catch here is the synthesizer I am working does not support the "new" keyword. The Synthesizer I am using translates C/C++ code to RTL code (Hardware).…
Nikhil Pratap
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for-loop synthesis in verilog

I saw an example beblow (people.tamu.edu/~ehsanrohani/ECEN248/lab5.ppt, Page39) about synthesis in verilog. module count1sC ( bit_cnt, data, clk, rst ); parameter data_width = 4; parameter cnt_width = 3; output [cnt_width-1:0] bit_cnt; …
Wayne
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Area optimization for a custom library using Synopsys Design Vision

I write a custom library for synopsys design vision which only consists of XOR, NOR, and IV (inverter or NOT). My plan is to synthesize a combinational logic such that the resulting netlist has minimum number of NOR gates. I write the library as…
ebi
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error in Assigning values to bytes in a 2d array of registers in Verilog .Error

Hi when i write this piece of code : module memo(out1); reg [3:0] mem [2:0] ; output wire [3:0] out1; initial begin mem[0][3:0]=4'b0000; mem[1][3:0]=4'b1000; mem[2][3:0]=4'b1010; end assign out1= mem[1]; endmodule i get…
user2307226
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Getting wrong results in post synthesis simulation

I am writing a code for Matrix Transpose in VHDL i am taking input in row major and one element of matrix per every clock cycle and i store the data in column major format after that i send tha data in coloumn major format element by element every…
Teja
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How to use the command "+incdir+" in synplify script(.tcl) when one verilog file include another verilog file?

I insert a verilog file into another verilog file by using "`include " And when I used the synplify script(*.tcl) to try to synthesize, one error occured: invalid command name "+incdir+<...>" It seems like I have to use the command "+incdir+"…
Xiuhua Yang
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What will this synthesize to in DC?

What will the be DC synthesis output? I don't have access to DC. If a=1 and b=1 will both address locations get updated ? Addr1 and addr2 are logic as well and guaranteed not to be equal. logic [3:0][31:0] cache; always_ff ....…
Rez
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Verilog for loop failed to synthesis using oasys

I have no idea why this piece of code failed to synthesis using oasys tool for (i = 0; i < N; i = i + 1) begin if( i >= counter & i < new_pos) out[i] <= bit; end where counter,out are reg and new_pos is wire for full…
Philopateer Nabil
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Circuit goes wrong when synthesized with a tight constraint

I have a RTL code. At first, I synthesized the circuit at 10 ns and run post-synthesis simulation. The circuit worked well. After that, I changed the timing constraint to 7 ns and re-synthesized the code using: compile_ultra -retime DC reported…
Kung Chu King
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Counting high of p showing average on d

module try2(p,d,q1,q2,q3,q4,q5,q6,q7,q8,c,a); input p,c; output [15:0]q1,q2,q3,q4,q5,q6,q7,q8,d,a; reg [15:0] d=16'b0;//may be error reg [15:0]a; always @ (posedge p) begin d<=d+1; end DFF dff0(q1,d,p); DFF dff1(q2,q1,p); DFF dff2(q3,q2,p); DFF…
Dipjyoti Das
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Exporting part of a circuit from a circuit defined as structural netlist in verilog

I have a gate-level structual netlist of a design with 40,000 gates and 5000 flipflops in verilog. It is a flattened netlist with no sub-circuits inside. I would like to extract another netlist from this large netlist by deleting a few flip-flops…
user2823269
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How to synthesis Rocket-Chip on Vivado?

I am trying to synthesis Rocket-Chip on Vivado. I was able to run a simulation on Vivado and get the required results. But, when I synthesis the same design and run the post synthesis simulation I dont get the same results. I used the 2 files…
hitoswal
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Sequential element is unused and will be removed from module in vivado

I am getting a warning that says [Synth 8-3332] Sequential element (\i_data_1_vect_1_reg[31] ) is unused and will be removed from module cg_top in vivado. But the simulation is working fine. I would be great if someone shares why these warnings…
kuladeepsai reddy
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