-3

I am trying to synthesis Rocket-Chip on Vivado. I was able to run a simulation on Vivado and get the required results. But, when I synthesis the same design and run the post synthesis simulation I dont get the same results. I used the 2 files generated after running 'make verilog' in vsim directory. For synthesis I defined the variable 'SYNTHESIS'. What are the things I might me missing go get appropriate results?

hitoswal
  • 11
  • 2

1 Answers1

0

You should generate Verilog output first, incorporate it into your system or SoC and then pass it to Vivado as usual

Tampler
  • 385
  • 1
  • 9
  • Thanks for the response @Templer. Yes I am generating the verilog files first. In my case the are named as "freechips.rocketchip.system.DefaultConfig.behav_srams.v" and "freechips.rocketchip.system.DefaultConfig.v" and then building a Vivado project using these files. I am able to simulate on Vivado using these files but when I synthesis and run post synthesis simulation, I get completely results then expected. – hitoswal Nov 13 '18 at 01:12