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I saw an example beblow (people.tamu.edu/~ehsanrohani/ECEN248/lab5.ppt, Page39) about synthesis in verilog.

module count1sC ( bit_cnt, data, clk, rst );
    parameter data_width = 4;  parameter cnt_width = 3;
    output [cnt_width-1:0] bit_cnt;
    input   [data_width-1:0] data;  input clk, rst;
    reg [cnt_width-1:0] cnt, bit_cnt, i; reg [data_width-1:0] tmp;
    always @ ( posedge clk )
        if ( rst ) begin cnt = 0; bit_cnt = 0; end
        else begin
        cnt = 0; tmp = data;
        for ( i = 0; tmp; i = i + 1 )
            begin if ( tmp[0] ) cnt = cnt + 1; 
                tmp = tmp >> 1; end
        bit_cnt = cnt;
    end
endmodule

Actually, this is an example for Not Synthesizable, but it seems like a synthesizable case, at least through Design compiler. Maybe the data_width has only 4 bits. If I change the data_width to 5, it will fail (out of iteration limits).

Can anybody explain this for me? Thanks in advance!

mcleod_ideafix
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Wayne
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1 Answers1

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It is not synthesizable. The number of times that the for loops is not known at compile time. Recall that the for condition has tmp, which is initialized with data whose value we don't know at compile time.

In order for this code (or any other) to be synthesizable, the compiler must be able to unroll the loop. If you see this code and cannot calculate how many times the block inside the for must be instantiated, the compiler won't either.

mcleod_ideafix
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  • Thanks for your reply. I know this is what the slides mean, but when I try to synthesize this through Design Compiler I found that it is synthesizable and I will get a reasonable netlist finally. – Wayne Apr 19 '15 at 20:57