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Questions tagged [synthesis]

Synthesis turns a high level circuit description into an implementation in logic gates.

Synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL) described in VHDL or Verilog, is turned into a design implementation in terms of logic gates.

Wikipedia

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using values instead of pointers as function arguments

I have this function "cost_compare" that I would like to offload on FPGA for some experimental purposes. This function, how it is called and its arguments are as follows. The synthesis tool doesn't accept double pointers as arguments for HW…
Hooman
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Using Verilog Case Statement With Continuous Assignment

I'm trying to perform continuous translation in Verilog from some greycode values to some binary values. That is, I'm trying to take a greycode value coming in on one bus and continually translate it to a binary value on another bus. I'm trying to…
Mindigo
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Array indexes to wide for array

I have the following problem when accessing arrays in VHDL: Say I have an array which is not of size 2^n, for example of size 6. Then, if I want to access this array using an index of width 3 bits (=ceil(log2(6))), it is clear that this index can…
Klowse
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how to track errors in FPGA/ASIC development using post place'n' route and/or post synthesis simulation?

I am a bit confused on the usefulness of post PnR and/or post synthesis simulations for FPGA/ASIC development. If the synthesis or PnR process complete successfully in the design flow, is there any chance that the respective 'post' simulation will…
user2609910
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what is the main difference between project mode and non project mode in vivado?

And when the synthesis is completed i am getting many files like .fw, .mcs, .prm along with .bit file, and can we dump those other files other than .bit file into FPGA? Which one is more advantageous project mode or non project mode? Coding is done…
vlsi_user
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Illegal syntax for subtype indication VHDL200X

I am trying to create a "dynamic" 2D array which I can set with generics in my entity. I followed the example in…
MVT
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Why do we use Blocking statement in Combinatorial Circuits designed using Always Block in Verilog/Systemverilog ? Why not Nonblocking?

Everywhere it is mentioned this as a guideline, but after lot of thought i want to know what harm will it cause if we use Nonblocking statement inside Always Block for Combinatorial also. I won't be mixing the two together. But what i feel is when…
Edwin Joseph
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Logic synthesis from an arbitary piece of code

I have completed on a project making physical logic gates and am now looking for a way to turn an arbitrary program into some series of logic gates so I can use them. I need a program that can take some arbitrary function (say f= x^2 -1) directly…
Josh Ketts
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Can I synthesize a parameterized function in systemverilog where structure is used as a parameter?

I was trying to synthesize a parameterized function where a structure is given as a parameter. I get the following error in the beginning of the parameterized function "Syntax error at or near token 'virtual'." I was trying to compile this simple…
Shahriar
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How do I get rid of sensitivity list warning when synthesizing Verilog code?

I am getting the warning that: One or more signals are missing in the sensitivity list of always block. always@(Address)begin ReadData = instructMem[Address]; end How do I get rid of this warning?
aherlambang
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Booth's algorithm Verilog synthesizable

I am trying to implement Booth's algorithm (a finite state machine implementation) for a Xilinx FPGA. Basically, at the start signal I will initialize my auxiliary regs, then I will go in state 0, where I will start to compare the 2 bits and do the…
Silent Control
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Synthesis in Programming; What is it exactly?

Currently I am reading a book about Software Development Engineering. In the chapter one of this book it says: Synthesis is a productivity mechanism for developing software by which the implementation is generated rather than created manually. It…
Hamidreza Soleimani
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Is it possible to play synthesized sound in the browser using JavaScript?

I just came across a Nintendo emulator written entirely in JavaScript on the interwebs, but it doesn't have sound. It got me thinking: Is there any way to synthesize sound in the browser using JavaScript and then play it? If it's not possible in…
PeterAllenWebb
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Data structure for Assembly audio synthesis

I'm writing a simple synth in assembly as a learning project, and I'd like to implement a few more advanced features found on modern synths, namely the ADSR envelope and pulse width modulation using a sine wave. At the moment, I'm basically…
dmkc
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.net synthesizer

I'm looking for a synthesizer that I can integrate with my .NET application. Is there any .NET synthesizers available out there? Is there a way of integrating VST-plugins into your .NET application? I want to create sounds based on MIDI-input,…
Pking
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