Stack Overflow
Stack Overflow

Questions tagged [synthesis]

Synthesis turns a high level circuit description into an implementation in logic gates.

Synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL) described in VHDL or Verilog, is turned into a design implementation in terms of logic gates.

Wikipedia

423 questions
7
votes
1 answer

What is "gate count" in synthesis result and how to calculate

I'm synthesizing my design with design compiler and have some comparison with another design (as a evaluation in my report). The Synopsys's tool can easily report the area with command but in all paper I've read care about gate count. My quiz is…
Khanh N. Dang
  • 906
  • 1
  • 9
  • 18
7
votes
2 answers

SystemVerilog: Passing interfaces to functions/tasks (for synthesis!)

Is there any synthesizable way to pass an interface to a function or a task? My use case is the following: I have a package with several functions (though I could convert them to tasks, if that helps :) ), all of which might be used in a module and…
rainer
  • 6,769
  • 3
  • 23
  • 37
6
votes
4 answers

VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)?

Say I need a signal to represent numbers from 0 to 5; obviously this needs 3 bits of std_logic to be represented (i.e if MAXVAL=5, then bitwidth= {wcalc "floor(logtwo($MAXVAL))+1"}). I'm aware I could do: SIGNAL myLogicVector : STD_LOGIC_VECTOR(2…
sdaau
  • 36,975
  • 46
  • 198
  • 278
6
votes
2 answers

Lattice ICE5LP4K FPGA: How to add HFOSC to user vhdl

I'm having trouble using the internal oscillator for the Lattice ICE5LP4K. Per the iCE40 Oscillator Usage Guide Appendix, the code in verilog should look like this: SB_HFOSC OSCInst0 ( .CLKHF_EN(ENCLKHF), …
Rob
  • 121
  • 1
  • 7
6
votes
5 answers

Sound chords in C#?

I've tried using Console.Beep() at low millisecond rates two play two frequencies 'at once', but the pause between beeps ruins it. I have tried researching it but I've found nothing, and don't know where to start, aside from DirectSound, which I'm…
apophis
  • 65
  • 5
6
votes
2 answers

How to synthesize piano sounds in android/java

I have made a few simple apps on android, and thought it was time for something a bit more complex. So, i thought I'd try something that's already out there, but build it from scratch. The idea is to create an app that allows user to play piano by…
Abid Ullah
  • 155
  • 2
  • 10
5
votes
4 answers

Sound synthesis with C#

Is there some possibility to generate sounds in C#? I mean not just beep or open and play wave-file. I mean build the signal using different kinds of waves (sin, saw, etc.) and their options (frequencies, amplitudes, etc.)
Mr.D
  • 225
  • 1
  • 6
  • 15
5
votes
3 answers

combinatorial hardware multiplication in verilog

Suppose I have a multiplier code like this, module multiply( output [63:0] result, input [31:0] a, input [31:0] b ); assign result = a * b; endmodule This produces a lot of gates. What preferable…
e19293001
  • 2,783
  • 9
  • 42
  • 54
5
votes
3 answers

Does the synthesizer care about one or two processes?

There are two popular ways of coding a state machine in VHDL: one process or two processes. There are rumors (and it is taught in some colleges) that two processes might result in better hardware. Does anybody have any hard evidence for this? My own…
Philippe
  • 3,700
  • 1
  • 21
  • 34
5
votes
2 answers

Synthesisable Fixed/Floating points in VHDL's IEEE Library

I'm creating a VHDL project (Xilinx ISE for Spartan-6) that will be required to use decimal "real-style" numbers in either fixed/floating point (I'm hoping fixed point will be sufficient). Being quite new to VHDL, I found out the hard way that the…
davidhood2
  • 1,367
  • 17
  • 47
5
votes
3 answers

VHDL synthesis warning FF/Latch has a constant value of 0

I'm trying out some code that essentially involves using an FPGA and reading values from a temperature sensor. The code is below: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----…
Triple777er
  • 621
  • 3
  • 17
  • 30
4
votes
2 answers

Concatenating synthesized tones in python

I'm using the following code which will generate a wav file which contains a tone at 440 Hz lasting for 2 seconds. from scipy.io.wavfile import write from numpy import linspace,sin,pi,int16 def note(freq, len, amp=1, rate=44100): t =…
Alex Coplan
  • 13,211
  • 19
  • 77
  • 138
4
votes
1 answer

How to interface Java midi to other applications

Hi I am programming Java on Windows and am very new to working with MIDI interfaces. I have managed to get java to play midi sounds through Synthesizer objects, natively through the computers speaker however I wish to send midi messages on the fly…
Skip Adam
  • 43
  • 3
4
votes
5 answers

How to synthesize sounds of instruments on Android (Piano, Drums, Guitar, etc...)

Can somebody give me some direction on how to synthesize sounds of instruments (Piano, Drums, Guitar, etc...) I am not even sure what to look for. Thanks
bobetko
  • 5,019
  • 14
  • 58
  • 85
4
votes
4 answers

Resources for logic synthesis and verification

I am currently working on logic synthesis- given a high level description of a hardware I wish to convert it into a circuit of gates,flip flops etc. I am not very much familiar with the theory. I searched the internet, but most of them refer to…
Adwaitvedant
  • 253
  • 3
  • 10
1
2
3
…
28 29