I have a RTL code. At first, I synthesized the circuit at 10 ns and run post-synthesis simulation. The circuit worked well. After that, I changed the timing constraint to 7 ns and re-synthesized the code using:
compile_ultra -retime
DC reported that the circuit has met timing requirements (slack = 0) and there is no design rule violation either. However, the netlist couldn't pass post-synthesis simulation. Does anyone know why?
I have found that Xilinx gate level simulation have (had?) a flaw when running at very high frequencies. This was 10+ years ago so things might have changed!
In my case I was simulating logic running at 300MHz. The results where baffling so I pulled in the most important signals in the waveform display.
The problem turned out to be the clock. The delay in the clock tree is simulated by lumping all the delay in the IBUF buffer. The clock tree behaviour is that of a net- or transport delay: The pulse going in will come out after a while. The IBUF delay model should therefore use a non-blocking delay:
always @( I)
O <= #delay_time I;
But it does not. Instead it uses a standard O = I; blocking statement which gets SDF annotated.
Thus if the high/low period of the input frequency to the buffer is longer then the IBUF delay, clock edges get lost and your gate level simulation fails.
I don't know if Xilinx have fixed that but I would say check your clock.
