Verilog Is this synthesizable read from array

Question

Is the following code synthesizable?

reg [15:0] litlen_buff0[3:0];
reg [1:0]  rcount0;

assign litlen_buff0_out = litlen_buff0[rcount0];

Answer 1

Yes, such construct like this is synthezisable if litlen_buff0_out is properly declared as output/inout or signal.

Signal can be used as array index as long as array slice has constant size. For example this code:

reg [15:0] litlen_buff0[3:0];
reg [1:0]  rcount0;

assign litlen_buff0_out = litlen_buff0[rcount0 : 0];

is not synthezisable because synthesis tool don't know exact size of right hand operand.