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I insert a verilog file into another verilog file by using "`include " And when I used the synplify script(*.tcl) to try to synthesize, one error occured:

invalid command name "+incdir+<...>"

It seems like I have to use the command "+incdir+" according to online documents, but what something wrong happened?

Example page 365

If your project has Verilog files with `include statements, you must use
the +incdir+ <file name> argument when you specify the vlogan
command. You enter the +incdir+ in the Verilog Compile field in the VCS
Options dialog box, as shown below:
Mikef
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Xiuhua Yang
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  • +incdir+ does not include anything. It only specifies directories where compile looks for files from `include statements. Other than that you should provide more info about your issues. – Serge Aug 08 '23 at 18:04

1 Answers1

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quoting from the documentation : if you have an include file,

`include "component.v"
module Top (input a, output x);
...
endmodule

you need to tell the relative directory of the include file (component.v) with respect to the directory of synplify script(.tcl) :

vlogan -work work Top.v +incdir+ ./ +incdir+ ../include_dir1

etc.

Mustafa Hakan Solmaz
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  • Your answer could be improved with additional supporting information. Please [edit] to add further details, such as citations or documentation, so that others can confirm that your answer is correct. You can find more information on how to write good answers [in the help center](/help/how-to-answer). – Community Aug 17 '23 at 02:35