Why doesn't the simplest example work (VHDL, Quartus)?

Question

Here is my VHDL code:

entity test is
    port (
        x1, x2 : in bit;
        f     : out bit
    ); 
end test;

architecture behavior of test is
begin
    f <= x1 and x2;
end behavior;

In Quartus (v. 18.1) I go to File->New->University Program VWF. In Simulation Waveform editor, I go to edit->insert->insert node or bus->node finder, push 'list' and select all nodes (in this case x1, x2, and f). Then I go to Simulation->Run functional simulation and get the error:

# ** Fatal: (vsim-3807) Types do not match between component and entity for port "f".

Do I need to change the type of port "f" in the component somewhere on Quartus, or what?

The error is not in the code shown, but in the testbench or upper level of the design. The component you have written is not using the type `bit` in the component declaration. — Tricky, Jun 16 '23 at 15:17
@Tricky, how can I change component declaration? I have only 2 files. The first file whith code above and the second is .vwf file. In .vwf file port 'f' has binary radix. — Vladimir Korshunov, Jun 16 '23 at 16:06
This a tool usage problem and not a VHDL issue. The Modelsim vsim error is the result of depending on an unsophisticated tool generating a testbench (in a .vho or .vht file) from your waveform description in Quartus likely expecting you to be be using std_logic based port signals. There are several options. Write your testbench yourself, switch to using std_logic or write a translation layer converting between type bit and type std_logic. You might also explore the limitations of the waveform interfacing software by reading documentation and/or following a tutorial. — user16145658, Jun 16 '23 at 18:15

score 1 · Answer 1 · answered Jun 17 '23 at 09:20

The simplest way to solve this problem - use std_logic instead of bit. Here is working code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test is
port (x1, x2: in std_logic;
        f: out std_logic); 
end test;

architecture behavior of test is
begin
f <= x1 and x2;
end behavior;

Why doesn't the simplest example work (VHDL, Quartus)?

1 Answers1