Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of fpga and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also: altera

554 questions

votes

1 answer

Trying to find Fmax in VHDL but getting extra cycle of delay

I want to see the speed of my VHDL design. As far as I know, it is indicated by Fmax in the Quartus II software. After compiling my design, it shows an Fmax of 653.59 MHz. I wrote a testbench and did some tests to make sure that the design is…

vhdl intel-fpga quartus

asked Jul 26 '16 at 12:52

gilianzz

votes

0 answers

Cannot use component in function

Assignment: Write a package declaration that declares: 1) (25 Pts) User defined type for BCD (Binary Coded Decimal) for 4 digit decimal numbers (In BCD notation four bits are used to indicate a decimal digit. Hence, the two digit decimal number…

vhdl intel-fpga quartus

asked Jul 10 '16 at 17:00

user3720045

votes

2 answers

Measure Power Consumption of Designed system on an Altera DE1 Board

I am designing a processor using an Altera DE1 kit. I will be running test bench to stress the processor. I want to know if there is any way to measure only the power consumption of my design and neglecting the other power dissipation caused by the…

fpga intel-fpga quartus

asked Jul 05 '16 at 08:13

Adaptive

votes

1 answer

Maximum frequency of my FPGA design in Quartus (Altera)

I've been told that during compilation maximum frequency of the compiled design is estimated and can be viewed somewhere in logs - my problem is, I cannot find it. Any idea to where it's located in Quartus 13.0? Screenshot would be great, thanks in…

fpga intel-fpga quartus

asked Jul 03 '16 at 12:52

Benji

votes

4 answers

In Verilog, I'm trying to use $readmemb to read .txt file but it only loads xxxxx (dont cares) on memory

I need to load a memory with some data originally in binary. I read that $readmemb can be use for this, and there is even a method to make synthesizable. So, I created another module named RAM_IN (which is not the testbench module) and "connected"…

memory verilog quartus test-bench

asked May 10 '16 at 10:28

sujeto1

votes

1 answer

VHDL: conv_std_logic_vector parameter error

I'm having some problems with the conv_std_logic_vector function in Quartus. I'm using the function to convert a integer variable into a std_logic_vector. When i compile the code below, Quartus shows the following error message: Error (10344):…

parameters vhdl quartus

asked Apr 30 '16 at 20:54

user5410082

votes

2 answers

compiling fphdl in Altera Quartus Prime

i tried to compile my design that uses fphdl libraries http://www.eda.org/fphdl/ for floating point operations. While in modelsim simulation is fine when synthesizing in Quartus hdl compiler complains about the statement: result := to_integer (fract…

vhdl point floating quartus

asked Feb 27 '16 at 13:17

user2609910

votes

1 answer

VHDL standard layout & syntax for "header" file

IDE: Quartus 15 I'm new to VHDL programming so there are some nuances I am not used to (translating from C++). Whilst I have found resources for programming the "source" files, I've struggled to find anything for the "header" files. In short, what…

vhdl header-files quartus

asked Feb 05 '16 at 21:45

user3303504

votes

2 answers

Does not work as before Verilog initial construction in ModelSim Altera Edition 10.4

Since version 10.4, start problem with initial block. Like this: reg [31:0] init_ram[15:0]; initial begin init_ram[0] = 32'h1234_5678; init_ram[1] = 32'h8765_4321; ... end always_ff @(posedge clk) init_ram[addr] <= data; Or module…

verilog system-verilog modelsim intel-fpga quartus

asked Jan 18 '16 at 08:29

Papayaved

votes

1 answer

RTL Viewer Command line

What is the command to run Alter Quartus RTL Viewer, or ModelSim RTL from the Command line under Windows? I tired the following command, however RTL Viewer window does not appear quartus_rpp t -c t --netlist_type=sgate where t is my project's name…

modelsim intel-fpga quartus

asked Dec 12 '15 at 16:05

Haskell00

votes

1 answer

How to initialize signal using .mif file

For example, I have behavioral definition of ROM: ENTITY rom_4x4_behavioral IS PORT (address : IN NATURAL RANGE 0 TO 7; q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END entity; ARCHITECTURE rom_4x4_behavioral_arch OF…

initialization vhdl quartus

asked Nov 24 '15 at 00:57

Alter Me

votes

2 answers

wait statement must contain condition clause with UNTIL keyword

The following VHDL is to be used to test bench. I keep getting an error on the first wait statement during analysis : "wait statement must contain condition clause with UNTIL keyword" I have several working test benches written this way. I can't…

vhdl intel-fpga quartus

asked Nov 18 '15 at 14:15

aviv yaakobi

votes

1 answer

Using De2-115 board to run a project developed on a different board?

I am trying to run different open source projects/games on my DE2-115 Altera board, however, these projects are usually developed on different boards like: Xilinx Spartan 3, DE0, DE1, ...etc. My question is, what are generally the things I need to…

vhdl verilog fpga intel-fpga quartus

asked Nov 15 '15 at 13:56

newbie

votes

1 answer

Modelsim Testbench not generating console output

I've designed a unit for my homework here, module homework1(a, b, sel, y); input signed [7:0] a, b; input [1:0] sel; output reg signed [7:0] y; always @(a or b or sel) begin case (sel) 2'b00: y = a + b; 2'b01: y = a - b; …

verilog modelsim quartus

asked Oct 24 '15 at 17:10

Shane Hsu

7,937
6
39
63

votes

1 answer

Is an inferred latch in Quartus II necessarily transparent

I have a module that should represent a "distributed RAM", where multiple registers can be written in parallel and read through a single MUX. A minimal example would be: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity…

vhdl fpga synthesis quartus

asked Jun 09 '15 at 09:03

mbschenkel

1,865
1
18
40

Prev 1 2 3

…

36 37 Next