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Getting some strange errors when I try to compile my code onto my DE2 board using Quartus. My friend has tried my code on his computer and it compiles without error, however on mine, it gives me the following errors.

Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sun May 17 15:11:37 2015
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 353lab2 -c lab2
Warning (20028): Parallel compilation is not licensed and has been disabled
Error (10430): VHDL Primary Unit Declaration error at std_logic_1164.vhd(51): primary unit "std_logic_1164" already exists in library "ieee"
Error (10784): HDL error at std_1164.vhd(46): see declaration for object "std_logic_1164"
Error (10430): VHDL Primary Unit Declaration error at syn_unsi.vhd(34): primary unit "STD_LOGIC_UNSIGNED" already exists in library "ieee"
Error (10784): HDL error at std_logic_unsigned.vhd(30): see declaration for object "STD_LOGIC_UNSIGNED"
Error (10431): VHDL Secondary Unit Declaration error at std_logic_1164.vhd(252): secondary unit "std_logic_1164" already exists in primary unit "std_logic_1164"
Error (10784): HDL error at std_1164.vhd(246): see declaration for object "std_logic_1164"
Error (10523): Ignored construct STD_LOGIC_UNSIGNED at std_logic_unsigned.vhd(87) due to previous errors
Error (10523): Ignored construct VITAL_Timing at timing_b.vhd(54) due to previous errors
Error (10523): Ignored construct LPM_COMPONENTS at lpm_pack.vhd(678) due to previous errors
Error (10523): Ignored construct std_logic_arith at mgc_arit.vhd(270) due to previous errors
Error (10523): Ignored construct qsim_logic at mgc_qsim.vhd(755) due to previous errors
Error (10523): Ignored construct TEXTIO at textio_vhdl93.vhd(103) due to previous errors
Error (10523): Ignored construct std_logic_arith at syn_arit.vhd(204) due to previous errors
Error (10523): Ignored construct std_logic_misc at syn_misc.vhd(182) due to previous errors
Error (10523): Ignored construct STD_LOGIC_SIGNED at syn_sign.vhd(95) due to previous errors
Error (10523): Ignored construct std_logic_textio at syn_textio.vhd(68) due to previous errors
Error (10523): Ignored construct STD_LOGIC_UNSIGNED at syn_unsi.vhd(93) due to previous errors
Info (12021): Found 2 design units, including 1 entities, in source file lab2.vhd
    Info (12022): Found design unit 1: lab2-impl
    Info (12023): Found entity 1: lab2
Info (12021): Found 2 design units, including 1 entities, in source file dflip.vhd
    Info (12022): Found design unit 1: dFlip-impl
    Info (12023): Found entity 1: dFlip
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 17 errors, 1 warning
    Error: Peak virtual memory: 529 megabytes
    Error: Processing ended: Sun May 17 15:11:38 2015
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01

From what I understand, Quartus is possibly detecting multiple copies of std_logic_1164 in "ieee", however when I click the error loation, it takes me to quartus/libraries/ieee/std_logic_1164.vhd.

Qiu
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    See Quartus Help [ID: 10430](http://quartushelp.altera.com/13.1/mergedProjects/msgs/msgs/evrfx_vhdl_primary_unit_exists.htm). Somewhere you have inadvertently told your synthesis tool (quartus_map) to build packages std_logic_1164 and std_logic_unsigned. The file std1164.vhd is the synthesis version of std_logic_1164 and syn_unsi.vhd is the synthesis version of std_logic_unsigned. None of these should require synthesizing. You may have a scripting error (including things in your project you shouldn't) or configuration (tool installation) error. –  May 17 '15 at 23:49
  • Just did a complete reinstall of Quartus and Modelsim, and am still getting the same error. I have no idea how this would have occurred as I am very careful about mucking around in project files. –  May 18 '15 at 01:07
  • Maybe double check your Quratus install. Specifically look in quartus\libraries for duplicate directories/files. You said that the tool takes you to _quartus/libraries/ieee/std_logic_1164.vhd_ when clicking on the error. However my 13.1 install has that package under _quartus/libraries/vhdl/ieee/std_1164.vhd_. Also make sure you don't have the library referenced in one of the locations the [tool looks before](http://quartushelp.altera.com/13.1/mergedProjects/global/pjn/pjn_tab_user_lib.htm) checking quartus/libraries. – pwolfsberger May 19 '15 at 04:24
  • Was your code generated using Qsys system? – Qiu May 19 '15 at 08:49

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