am trying to make code in verilog Quartus for 8-bit 2x1 MUX but i have errors in the code

Question

module muxx(M, X, Y, S, SW,LEDR,LEDG)    
(
input [17:0]X,
 input [17:0]Y,
output [15:0]LEDR,
output [7:0]LEDG,
output [7:0]M
);
if
S=0;
M=X;
while if
S=1;
M=Y;
wire [7:0] X = SW[7:0];
wire [7:0] Y = SW[15:8];
wire S = SW[17];
input SW[17];
input[17:0]SW;
muxx ex(.M(LEDG), .S(SW[17]), .X(SW[7:0]), .Y(SW[15:8]));
assign LEDR[7:0] = X;
assign LEDR[15:8] = Y;
assign M[0] = X[0] & ~S | Y[8] & S;
assign M[1] = X[1] & ~S | Y[9] & S;
assign M[2] = X[2] & ~S | Y[10] & S;
assign M[3] = X[3] & ~S | Y[11] & S;
assign M[4] = X[4] & ~S | Y[12] & S;
assign M[5] = X[5] & ~S | Y[13] & S;
assign M[6] = X[6] & ~S | Y[14] & S;
assign M[7] = X[7] & ~S | Y[15] & S;
 endmodule

I study NCE and am taking course in SE, and I don't know how to code this MUX 2-to-1 8-bit I tried to code but I got these errors:

Error(13411): Verilog HDL syntax error at MUXX.v(3) near text (
Error: Flow failed:
Error: Quartus Prime Synthesis was unsuccessful. 2 errors, 0 warnings
    Error: Peak virtual memory: 4972 megabytes
    Error: Processing ended: Tue Oct 16 20:53:12 2018
    Error: Elapsed time: 00:00:03
    Error: Total CPU time (on all processors): 00:00:03
Error(293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 0 warnings

Answer 1

You have actually mixed two different port declarations styles, see IEEE1800-2017, ch. 23.2. You need to choose, which one you want to use.

ANSI style:

module muxx   
(
   input [17:0] X,
   input [17:0] Y,
   output [15:0] LEDR,
   output [7:0] LEDG,
   output [7:0] M
);
//...
endmodule

Non-ANSI style:

module muxx(M, X, Y, S, SW,LEDR,LEDG);   
   input [17:0] X;
   input [17:0] Y;       
   output [15:0] LEDR;       
   output [7:0] LEDG;
   output [7:0] M;
//...
endmodule