Why is this variable not considered a constant?

Question

The following is code I wrote is a test bench to simulate a decoder (Verilog HDL). It converts [15:0]IR to [25:0]ControlWord. Literal is a byproduct that is watched as well.

All values from 0-65535 need to be tested for the 16-bit IR variable. In the beginning of the loop, I distinctly assign IR to be 0, but Quartus is telling me that:

Warning (10855): Verilog HDL warning at controluni_tb.v(20): initial value for variable IR should be constant

and as a result I get the following:

Error (10119): Verilog HDL Loop Statement error at controluni_tb.v(23): loop with non-constant loop condition must terminate within 250 iterations

The code for my test bench module is as follows:

module controluni_tb;
  reg [15:0]IR;
  reg clock;
  wire [25:0]ControlWord;
  wire [15:0] literal;
  Total_Control_Unit_2 dut (IR,ControlWord,literal);

  initial
  begin
    clock <= 1'b0;
  end

  initial
  begin
    IR <= 16'b0;
  end

  initial
  begin
    forever
    begin
      #1 IR <= IR + 16'b1;
    end
  end

  initial
    #65535 $finish;
endmodule

Amir · Answer 1 · 2015-04-26T08:56:11.177

0

Your code has no errors. initial blocks and system functions ($finish) is used for simulation (not synthesis). That error is related to synthesis. I edited your code for more readability (your clock is always zero!) :

module controluni_tb;
    reg [15:0]IR;
    reg clock;
    wire [25:0]ControlWord;
    wire [15:0] literal;

    Total_Control_Unit_2 dut (IR,ControlWord,literal);

    initial begin
        clock = 1'b0;
    end

    initial begin
        IR = 16'b0;
        forever #1 IR = IR + 16'b1;
    end

    initial begin
        #65535 $finish;
    end
endmodule

edited Apr 26 '15 at 08:56

answered Apr 26 '15 at 06:09

Amir

507
3
12

I understand, but this code is meant to be a simulation. However, before I simulate in ModelSIM, Quartus requires me to run an Analysis & Synthesis on the code. It is when I run that I receive the aforementioned errors. – user3571270 Apr 26 '15 at 19:17
Ok, so Quartus checks the synthesis limitations before simulation. But you can set the loop limit in the Quartus Settings File (.qsf). See [Error (10119) : Verilog HDL Loop Statement error](https://www.altera.com/support/support-resources/knowledge-base/solutions/rd04232012_554.html) – Amir Apr 26 '15 at 20:08
I have tried that by setting the limit to both 100,000 and 1 million. Both errors appear again. – user3571270 Apr 26 '15 at 20:48

score 0 · Answer 2 · answered Apr 27 '15 at 16:11

0

Instead of using a forever loop, why not just use a for loop for IR? Then the problem is completely bounded.

initial begin
    for (IR = 0; IR <= 65535; IR++);
    $finish;
end

answered Apr 27 '15 at 16:11

Barry Moss

509
1
4
14

That fixed the loop error, but now I am receiving the error: Error (12061): Can't synthesize current design -- Top partition does not contain any logic – user3571270 Apr 28 '15 at 02:50
OK, if you want synthsizable logic, you shouldn't be using initial statements (keep those for testbenches). You need to make a clockable counter in an always block and provide a clock from your test bench to drive the circuit. – Barry Moss Apr 28 '15 at 20:36

Why is this variable not considered a constant?

2 Answers2