-1

Obligatory: I'm new to Verilog. I have two individual, working verilog modules: a nios-ii ADC and a counter module. The nios-ii controlled ADC qsys is properly instantiated in the main module. I am trying to instantiate the counter inside the main module as well. Quartus throws no errors, but nothing appears on the outputs where the counter should be outputting. The main module code is below:

module niosADCv2(

    input CLOCK,

    input ADC1IN1,          // Voltage Level 2.5 V
    input ADC1IN2,          // Voltage Level 2.5 V 

    input RESET_N               // Voltage Level 2.5 V
    );

niosADCv2_qsys u0 (
        .clk_clk       (CLOCK),       //   clk.clk
        .reset_reset_n (RESET_N)  // reset.reset_n
    );

verilog_counter verilog_counter_c0(
        .CLOCK          (CLOCK),
        .usec           (usec),
        .nsec           (nsec)
    );

endmodule

In a separate verilog file is my verliog_counter module:

module verilog_counter(CLOCK, usec, nsec);

input CLOCK;
output reg [7:0] usec; 
output reg [5:0] nsec; //counts by 20nsecs (50MHz clock)
wire CLOCK;

always @ (posedge CLOCK) 
if (nsec == 6'b110001) begin //if count is 49 (980ns)
nsec <= 7'b0; //reset 20nsec count
usec <= usec + 7'b1; //incriment usec count
end 
else nsec <= nsec + 8'b1; //if a usec not reached, incriment 20ns counter

endmodule

Any ideas why the counter output doesn't appear? Am I instantiating the counter module wrong or can I not have them in separate files? Any help is appreciated

Cup-0-Joe
  • 1
  • Thanks for the help, I ended up solving the issue. I didn't have variables in the top module that connected to nsec and usec. Once I made those variables and connected them in the instantiation, the outputs appeared correctly. – Cup-0-Joe Jun 15 '18 at 13:47

1 Answers1

0

You should add the declaration of usec and nsec in the top module. such as

reg [7:0] usec; 
reg [5:0] nsec;

and also add the file verilog_counter.v into the project.

kewei xia
  • 111
  • 1
  • 4