Basic Verilog Circuit Questions

Question

I'm trying to write a basic circuit in Verilog using Quartus Prime as a side project for a professor. That said, I'm having trouble with Verilog syntax. The circuit that I want to make is a collection of AND and OR gates that theoretically determine if an electric engine is to turn on. The engine will turn on if there is a) a foot on the break, b) the key is in the car, and c) there is sufficient charge on the battery. The enginer will also turn on if there is both a) charge on the battery, and b) The key is inserted into a secret slot. Unrealistic for a car design but it serves my purposes. First, my truth table:

The Engine Truth Table

And now, my code:

module ignition (
key,
foot,
batt,
secr,
powr,
);

//--INPUTS/OUTPUTS--
input key, foot, batt, secr;
output powr;

//--DATATYPE--
reg key, foot, batt, secr, powr

//--LOGIC--
always @ (posedge reset)
always begin
if (key == 1) && (foot == 1) && (batt == 1)
    powr == 1;
else if (secr == 1) && (batt == 1)
    powr == 1;
else
    powr == 0
end

//--TESTBLOCK--
module ignition_tb;

reg key, foot, batt, secr, powr

initial begin
    $monitor ("key=%b,foot=%b,batt=%b,secr=%b,powr=%b")
    key = 0
    foot = 0
    batt = 0
    secr = 0
    powr = 0

I'm not really sure where to go from here. Is my code set up properly for verilog? How do I implement testing?

Thanks!

you have an extra `always` in the code which follows the `always @...`. Get rid of it. — Serge, Nov 27 '18 at 19:42

score 0 · Answer 1 · answered Nov 29 '18 at 01:59

First things first, it would probably make sense to include a clock signal. Unless you want to trigger your logic on the posedge of a reset (which you may do, but unlikely).

As for issues in the code, you never define reset, your use of '==' to assign a value should be '<=', and you're missing lot's of semi-colons.

It's late, so this edit likely won't work, but it should give you some pointers.

module ignition (
key,
foot,
batt,
secr,
powr,
clk //clock input
);

//--INPUTS/OUTPUTS--
input key, foot, batt, secr;
output powr;

//--DATATYPE--
reg key, foot, batt, secr, powr;

//--LOGIC--
always @ (posedge clk) //assuming you want to use clock, else switch to whatever you want
if (key == 1) && (foot == 1) && (batt == 1)    
    powr <= 1;
else if (secr == 1) && (batt == 1)
    powr <= 1;
else
    powr <= 0;
end

//--TESTBLOCK--
module ignition_tb;

reg key, foot, batt, secr, powr, clk;

always @* begin
    #5 clk <= ~clk;
end

initial begin
    $monitor ("key=%b,foot=%b,batt=%b,secr=%b,powr=%b");
    key <= 0;
    foot <= 0;
    batt <= 0;
    secr <= 0;
    powr <= 0;
    //add some new values after a delay (#5) to test if it works.

Basic Verilog Circuit Questions

1 Answers1