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Questions tagged [quartus]

For questions about Quartus, a software tool developed by Altera / Intel to assist in the design, analysis, and synthesis of HDL designs, including FPGA and CPLD.

Quartus is a software tool produced by Altera / Intel for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

The Quartus design software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus software includes solutions for all phases of and CPLD design.

Source: Quartus II User Manual

QuartusHelp contains documentation about the list of messages that can output Quartus during synthesis with their signification.

See also:

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Export Data From USB Blaster of Altera DE1 Board and display data to UI

I am designing a processor using an Altera DE1 Board and I want to monitor some metrics like the clock frequency, register values, etc. I am planning to import data from the DE1's USB Blaster and display it in a UI designed in Windows Form. Is it…
Adaptive
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Two outputs values in a mod operation using vhdl

I am trying to do a circuit that get the MOD of two numbers, my problem is in the output of that circuit, the output shows 0 and then the correct value of MOD, i have to integrate this circuito to another circuit to do a circuito that shows if a…
Mutante
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VHDL 10500 : error syntax near text

I have this vhdl code : library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity avalon_fir_4 is port ( clk, reset: in std_logic; -- avalon interface gcd_address: in std_logic_vector(2 downto 0); -- 3-bit address …
ESD
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Load Counter Output Error on Simulation

I'm trying to do a load "counter", that works counting up the value from my input when load = 1, but i am having problems in the output, it seems to be a trash value on the output. I've used the partial solution from my old question here LIBRARY…
Mutante
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Integer to unsigned conversion going wrong VHDL quartus

I am having problem with an output error in a waveform, basically my code works as a counter, when i have a load signal equal '1' the counter goes up, if the load signal is '0' the counter doesn't counts. I have a clear signal to get the counter in…
Mutante
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LEON3 Processor on Quartus

I'm trying to use the LEON3 soft-core processor on an Altera device with Ubuntu. Is there anybody who has already used it ? Because, I choose my device and after I write 'make quartus' but I encountered the errors below: cp: cannot stat…
Aurélien Fourny
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Verilog Error unexpected '=', expecting identifier or type_identifier

I'm building a test bench night now, and I'm not sure how should I connect several modules I built earlier. Here's the modules I used, all of them were tested and works properly. counter11bit_abc ctr2(ctr_enable, ctr_clr, clk_out, counter); …
SYM2RR
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Testbench input 10500 Syntax Error

I tried to create a simple hello world testbench for a two input AND gate in Quartus. I am consistently running into the following error: Error (10500): VHDL syntax error at Scott_2InputAndGate_Test.vhd(19) near text "IN"; expecting an identifier…
scott morris
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Testbench not working

The following test bench fails to provide the intended signals for QAU and QBU : LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY VHDLfinal_vhd_tst IS END…
Nathan Piper
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VHDL Logical Simulation Error on add and shift Multiplier

I am trying to do an "add and shift multiplier (sequential)" and I am having problems on the final simulation, the value on the output goes always wrong. I've used a state machine logic to make the control block of the partial sums. When I make 1 x…
Mutante
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Encoder Debounce VHDL

For practice, I attempted to make a VHDL code to run Rotary encoder hardware. It was full with debounce, quadrature decoder and an up/down counter codes. Unfortunately, when running simulation with a testbench, my results were disappointing so I…
Nathan Piper
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Iteration limit when implementing a multicycled processor

I'm trying to implement a simple multicycle processor and I ran into some problems that I don't seem to be getting through. The code is below. I'm just experimenting right now to get this flowing. When I'm done, I'll begin implementing instructions…
Motun
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8 bits Array Multiplier VHDL (output wrong)

I'm trying to make a 8 bits Array Multiplier in VHDL, I am using the standard architecture of the array multiplier to do this, i have a BDF file receiving the A(multiplicand) and B(multiplier), and in this BDF file have a block named "adder" that…
user5410082
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VHDL - does this signal latch?

I have a module with D_IN_VAL std_logic_vector(n-1 downto 0) input port, and internal signal CUR_MAX_S : std_logic_vector(n-1 downto 0). I wish to use only parts of D_IN_VAL data (e.g 4 bits out of 20 bit signal) so I figured I'll 'save' D_IN_VAL in…
Benji
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Multiplexing more than 2 signals using Altera's LPM

How can I use busmux more than two input in Quartus? It seems I can use LPM_MUX instead, but I can't understand how to use it. Is there any easier way?
Alan42
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