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Hi I'm trying to use Qsys to create a PLL. The PLL is intended to be used with a serial interface on am FPGA. When I start Modsim to simulate. I get no output from the PLL. Investigating a bit further I tried to load just the PLL in modsim and I get the following error.

** Error: (vsim-3039) C:/altera/13.0sp1/____PROJECT____/TSSD/PLL/PLL1/synthesis/PLL1.vhd(49): Instantiation of 'PLL1_altpll_0' failed.
Region: /pll1 Error loading design

Of the 4 modules seen in the PLL1 entity see below:

enter image description here

Modsim will only except the bottom two. The "pll1_altpll_0" and "pll1_altpll_0_altpll_4242" modules display

Loading PLL1.PLL1_altpll_0_dffpipe_l2c Loading PLL1.PLL1_altpll_0_altpll_4242 ** Error: (vsim-3033) C:/altera/13.0sp1/____PROJECT____/TSSD/PLL/PLL1/synthesis/submodules/PLL1_altpll_0.v(192): Instantiation of 'cycloneiii_pll' failed. The design unit was not found.

When opened within modsim.

Has anyone had a similar problem or know where I am going wrong using either Modsim or Qsys?

Many Thanks D

hoboBob
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  • Possible duplicate of [VHDL - DE0 - QUARTUS II PLL not showing output in modsim](http://stackoverflow.com/questions/35297697/vhdl-de0-quartus-ii-pll-not-showing-output-in-modsim) – Martin Zabel Feb 22 '16 at 00:47
  • Did you used a testbench this time? – Martin Zabel Feb 22 '16 at 00:48
  • No its different, please read the post mr Zabel, – hoboBob Feb 22 '16 at 07:19
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    I see no difference because I see no testbench. And in [my answer](http://stackoverflow.com/a/35309736/5466118) to your other question, I have clearly shown that one cannot simulate an Altera PLL without a testbench. – Martin Zabel Feb 22 '16 at 08:53
  • no you have not! and yes, you can, you have posted no answer, just shown that you can do make a pll, great good for you!. I would say that is why no one has marked it as a good answer. To clarify it for you. You have not answered the question – hoboBob Feb 22 '16 at 09:47

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