How to create synthesizeable delay?

Question

i got a code like below with clk = #10 ~clk

    always@ (posedge clk)begin
    for (g=0;g<8;g=g+1) begin
    ws = 1;
    #20
    ws = 0;
    #20;
    end

so is there any other way to make the delay 20 synthesizaeble in the coding above?

Delays are not synthesizeable. During synthesis, all the # delay statements are stripped of by the synthesizer. — vim, Mar 05 '16 at 07:22
What sort of hardware, electronic circuit are you trying to imply? If you consider this question you might realise why it is not possible, to give a constant delay across temperature and operating voltages. — Morgan, Mar 05 '16 at 09:15
hi morgan im trying to write data into ram by enabling and disable it and i saw the link you given but still had no idea how to put it in — Avelyn Goh, Mar 05 '16 at 09:24

score 0 · Answer 1 · answered Mar 05 '16 at 08:10

0

A flip-flop is the only way of synthesising a delay:

always @(posedge clk)
  q <= d;

With clk = #10 ~clk;, q will be #10 later than d.

answered Mar 05 '16 at 08:10

Matthew Taylor

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hi matthew the delay that i meant is the delay inside the always block because #20 cant be synthesize so i need other way to make the #20 synthesizeable – Avelyn Goh Mar 05 '16 at 08:49
@Avelyn Goh You need to think what (synthesis able) hardware can delay a signal. The answer is a flip-flop, that's it. What hardware would you expert to be synthesised from `#20`? – Matthew Taylor Mar 05 '16 at 11:03
yes i would like the #20 to be there when i synthesize but when i compile using quartus the #20 will be ignore so is there any other method to delay? – Avelyn Goh Mar 05 '16 at 11:14
2

If you want a delay of `#20` (assuming the timescale is set such that this means 20ns), you need a 50 MHz clock (or some harmonic) and some flip flops. There is no other method to delay. What other hardware could implement a delay of 20ns reliably? – Matthew Taylor Mar 05 '16 at 16:20

Morgan · Answer 2 · 2016-03-05T15:41:59.127

The question appear not to be how to synthesis a #20 but how to control the timing for signals in to a RAM. Digital design are based around clock edges, with each positive or negative edge a set distance a part, this is the period of the clock or 1/frequency.

To sequence events as you describe you need a FSM (Finite state machine) to control or sequence it. I have included a small example below:

Available on EDA Playground

module tb;

  //Tb component
  reg clk;
  reg rst_n;
  initial begin :clk_and_reset
    clk = 0;
    rst_n = 0;
    #40 rst_n = 1;
    #40;
    forever begin
      #20 clk = ~clk;
    end
  end

  //Design
  reg [1:0] state;
  reg [1:0] next_state;
  reg [31:0] counter;
  reg ws;

  localparam S_IDLE = 'd0;
  localparam S_WAIT = 'd1;
  localparam S_OFF  = 'd2;

  always @(posedge clk, negedge rst_n) begin
    if (~rst_n) begin
      state <= S_IDLE;
    end
    else begin
      case(state)
        S_IDLE : begin
          state   <= S_WAIT;
          counter <= 'b0;
        S_WAIT : 
          if (counter < 32'd10) begin
            state   <= S_WAIT;  //Wait for 10 clock cycles
            counter <= counter + 1;
          end
          else begin
            state   <= S_OFF;
            counter <= 'b0;
          end
        S_OFF :  state <= S_IDLE;
     default  :  state <= S_IDLE; //IDLE 
    end
  end


  //Output decode based on state
  always @* begin
    //ws goes high when in Wait state
    ws = (state == S_WAIT);
  end


  //Test program
  initial begin
    repeat (10) begin
      @(posedge clk);
      $display("%4t : State %b: ws :%b", $realtime, state, ws);
    end
    $finish();
  end


endmodule

This could be expanded by staying in idle until triggered then by having counter and staying in wait for x number of clocks, x number of clocks in OFF before going back to idle and waiting to be triggered again.

Update

I have updated the code example to stay in the WAIT state for 10 clock cycles to demonstrate how to control the delay between transitions.

hi morgan i think my problem is the same as this thread http://stackoverflow.com/questions/20865679/how-to-compare-integer-values-with-binary-in-for-loop-for-delay-generation-in-ve?lq=1 can i know whats the final answer for it? — Avelyn Goh, Mar 05 '16 at 13:43
@AvelynGoh I have updated the code example to stay in the **WAIT** state for 10 clock cycles to demonstrate how to control the delay between transitions. — Morgan, Mar 05 '16 at 15:42
hi sir i wanted to make like ws = 1 then it will delay for 20ns then only ws =0 and delay for 20ns if i use the code that you had provided i cant control it inside my for loop is there any other way? — Avelyn Goh, Mar 06 '16 at 03:56
Your for loop is un-synthesizable it needs to be controlled from a fsm, my original example showed it looping back and forth. It was easy to modify for a 50 50 duty cycle. There is no way to synthesize 20ns delay. But you can use flip-flop with a clock period of 20ns it is the only way. — Morgan, Mar 06 '16 at 05:52

How to create synthesizeable delay?

2 Answers2

Update