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I'm brand new to VHDL and the Quartus design environment, and I'm trying to run the simulation of some textio but I must be missing something... When I compile the following code (which I borrowed snippets of from an OSU VHDL textio guide (http://web.engr.oregonstate.edu/~traylor/ece474/vhdl_lectures/text_io.pdf), I get error 10533:

Error (10533): VHDL Wait Statement error at tio_top.vhd(36): Wait Statement must contain condition clause with UNTIL keyword

What type of condition is appropriate to use in this scenario? I've tried creating a condition that evaluates to a constant true or false, but that gives an error also. Perhaps my understanding of process is wrong and it needs to continuously run? Basically I just want to output variable a to a text file... Do I need to create a testbench?

library ieee;
library std;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.math_complex.all;
use ieee.std_logic_textio.all;
use std.textio.all;

entity tio_top is
end tio_top;

architecture main of tio_top is
begin
-----------------------------------------------------------------------------
  --practice with textio
  file_io: --declare a process for executing file input/output
  process is
    file out_file : text open read_mode is "out_values"; --declare output file name
    variable out_line : line; --declare variable of type line to store values
    variable a : std_logic; --declare other logic varialbes for playing around with     
  begin --put the meet of the textio here

    a := '1';

    write(out_line,a);
    writeline(out_file, out_line);

    wait; --allows simulation to halt!

  end process;

end main;
scary_jeff
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jakedaly
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    See [wait statement must contain condition clause with UNTIL keyword](https://stackoverflow.com/questions/33782358/wait-statement-must-contain-condition-clause-with-until-keyword). Are you trying to synthesis your VHDL design? You also can't write to a read_mode file. –  Aug 25 '17 at 01:36
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    Changing the out_values file declaration to write_mode, using a simulator and your code produces a file out_values containing the value `1`, despite all the superfluous use clauses. You're experiencing tool issues. –  Aug 25 '17 at 01:41
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    Quartus is a logic synthesizer. It does not accept the complete VHDL language but only a subset that makes sense for logic synthesis. Text file I/Os, pointers (the `line` type is an access type, the VHDL pointers) or the eternal `wait` statement are not part of this subset (what hardware would you expect?). – Renaud Pacalet Aug 25 '17 at 05:46
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    Wait statement in this process is right.But it is only for similation not for synthesize. – Liang He Aug 25 '17 at 10:03
  • If you want to simulate, use mentor graphics modelsim, "included" with the Intel/Alters tools. The Quatus ISE is for synthesis, not for simulation. – JHBonarius Aug 25 '17 at 18:21
  • @user1155120 Thank you! Instead of using NativeLink to import a simulator, I just took the file straight to ModelSim software and simulated there. – jakedaly Aug 27 '17 at 19:15

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