VHDL - Usage of high impedance

Question

I started learning VHDL and I'm current following a book instructions that suggested a 4 to 8 multiplexer with buffer. So I decided to build a 4x1 MUX. But I can't figure out how to set an individual output as high impedance.

LIBRARY ieee; 
USE ieee.std_logic_1164.all; 

ENTITY buffered_mux_4x1 IS 
    PORT (a, b, c, d: IN BIT;
        sel: IN NATURAL RANGE 0 TO 3;
        ena: IN BIT;
        y: OUT BIT);
END buffered_mux_4x1;

ARCHITECTURE myarch OF buffered_mux_4x1 IS
    SIGNAL x: BIT;
BEGIN
    x <= a WHEN sel=0 ELSE --MUX
         b WHEN sel=1 ELSE
         c WHEN sel=2 ELSE
         d;
    y <= x WHEN ena='1' ELSE -- Tristate buffer
          ???
END myarch;

Here's the original code to set the output at high impedance when the enable was set in '0':

LIBRARY ieee; 
USE ieee.std_logic_1164.all; 

ENTITY buffered_mux IS 
    PORT (a, b, c, d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        sel: IN NATURAL RANGE 0 TO 3;
        ena: IN STD_LOGIC;
        y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END buffered_mux;

ARCHITECTURE myarch OF buffered_mux IS
    SIGNAL x: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
    x <= a WHEN sel=0 ELSE --MUX
         b WHEN sel=1 ELSE
         c WHEN sel=2 ELSE
         d;
    y <= x WHEN ena='1' ELSE -- Tristate buffer
        (OTHERS => 'Z');
END myarch;

Here's the problem:

You should never use the type bit, but only std_logic and std_logic_vector. Then you can set y to 'z'. But you should never use tristate logic either if your target is an FPGA. Except by instantiating an external pad... — B. Go, Nov 22 '19 at 19:18
It worked! Thank you! I used this notation: `y <= x WHEN ena='1' ELSE 'Z' WHEN ena='0';` Is it all right? — Matheusarceu, Nov 22 '19 at 19:39
you're welcome! You don't even need the second when, actually. just else 'z' is fine — B. Go, Nov 22 '19 at 19:54
as long as you don't do crazy things with ena, like setting it to 'x' or 'z' — B. Go, Nov 22 '19 at 19:55
you should better avoid using x as a signal name, too, as 'x' is a signal value... — B. Go, Nov 22 '19 at 19:59
Type BIT is an enumerated character type with the values ('0', '1'). Type BIT isn't a resolved data type like std_logic. Resolution is taking the values of multiple drivers (the two concurrent signal assignments to `y`) and determining the effective value of the net `y`. It's illegal to have multiple drivers for a signal of a non-resolved data type. You can look in the source for package std_logic_1164 for std_logic and STANDARD (in the standard) for type BIT. The semantic of resolution for composite types has changed in -2008 (and IEEE packages are compatible). — , Nov 22 '19 at 21:21
You've provided most of a [mcve] but have neglected a description of the problem. Also, what book? — , Nov 22 '19 at 22:02
Thank you for the explanation. The book: Digital Electronics and Design with VHDL by Volnei A. Pedroni — Matheusarceu, Nov 22 '19 at 23:17

B. Go · Accepted Answer · 2019-11-24T22:02:55.730

1

with

y: OUT std_logic);

you can use

y <= x WHEN ena='1' ELSE 'z';

EDITS:
As commented by me and another user, the high impedance is not supported inside (most, if not all) FPGAs, even if the syntax is correct. It should rather be implemented with a vendor specific block at the pad.
You should forget about the BIT type, and never use it. std_logic(_vector), signed and unsigned are the normal logical values to use for synthesis. And a few other type like integer for bus sizes.
So indeed a, b, c, d, ena and x should also be std_logic(_vector). Depending where it comes from (is it an internal signal only?), sel too, even if a natural there might be interpreted correctly by some tools.

edited Nov 24 '19 at 22:02

answered Nov 22 '19 at 19:58

B. Go

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`x` shouldbe the same type or evaluated after type conversion. There are two concurrent signal assignments to `y` that should be combined. Note the Intel® Quartus® Prime Pro Edition User Guide Design Recommendations UG-20131 | 2019.11.0, 1 1.6.1. Tri-State Signals "Use tri-state signals only when attached to top-level bidirectional or output pins. ...synthesis software must push the tri-states through the hierarchy to the top level to make use of the tri-state drivers on output pins of Intel FPGA devices...." The OP doesn't describe the resulting *suggested a 4 to 8 multiplexer with buffer.* – Nov 22 '19 at 21:44

VHDL - Usage of high impedance

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