T FlipFlop Verilog

Question

I cannot get a T-Flipflop from a D flipflop to work in Modelsim even after it came directly from class notes. It must be something simple I'm just overlooking.

module D_FF (q, Clk, reset_n,d);
  output     q;
  input      Clk, reset_n, d;
  reg        q;

  always @(posedge reset_n or negedge Clk)
    if (~reset_n) 
       q <= 1'b0;
    else
      q <= d;
endmodule

module T_ff (q, Clk, reset_n);
   output q;
   input Clk, reset_n;
   wire d;

  D_FF DFF0 (q, Clk, reset_n, Vcc);
   not n1 (d,q);

endmodule

you got the functionality of a T flip-flop incorrect: https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#T_flip-flop — Greg, Feb 02 '16 at 04:46
Greg is correct, along with a few other things. First, your DFF should be using `negedge reset_n` as it is an asserted low reset. Second, you are connecting the `d` line of your DFF to non-existent wire `Vcc` (unless this is defined as a constant `1'b1` elsewhere, but that still doesnt help) — Unn, Feb 02 '16 at 06:05

score 1 · Answer 1 · answered Feb 08 '16 at 02:17

Hi there are two problems: 1. Your reset is active low, so it should be sensitive to the falling edge of the clock. 2. What is that VCC? you should use d there. Here is the correct version

D_FF:

module D_FF (q, Clk, reset_n,d);
  output     q;
  input      Clk, reset_n, d;
  reg        q;

always @(negedge reset_n or posedge Clk)
    if (~reset_n) 
       q <= 1'b0;
    else
      q <= d;
endmodule

T_FF:

module T_FF (q, Clk, reset_n);
   output q;
   input Clk, reset_n;
   wire d;

  D_FF DFF0 (q, Clk, reset_n, d);
   not n1 (d,q);

endmodule

T FlipFlop Verilog

1 Answers1