generate signal assignmen in vhdl

Question

I have a question. I want to use generate to signal assignment. but simulator takes me an error. the error is : " Illegal target for signal assignment." and "Unknown identifier A0_i."

architecure sss of fff is
signal A0_0 : bit ;
signal A0_1 : bit ;
signal A0_2 : bit ;
signal A0_3 : bit ;

begin

U0 : for i in 0 to 3 generate
U1 : A0_i <= a(i) and b(i) ;
end generate;

end sss;

Just make A0 an array of bits covering the range 0 to 3 and write the Generate to cover that range : `U0 : for i in A0'left to A0'right generate U1 : A0(i)<= a(i) and b(i) ;` — , Nov 04 '16 at 10:50
thank you. but i don't permit to change signal name. is there any way to solve this problem? — ali.329, Nov 04 '16 at 11:28
Provide alternate names for the signals - *IEEE Std 1076-2008 6.6 Alias declarations, 6.6.1 An alias declaration declares an alternate name for an existing named entity.* `signal A0: bit_vector ( 0 to 3); alias A0_0: bit is A0(0); alias A0_1: bit is A0(1); alias A0_2: bit is A0(2); alias A0_3: bit is A0(3);` and `U1: A0(i) <= a(i) and b(i);` The issue is that A0_i is an identifier, a non-divisible lexical element (15.3) while you want to use an indexed name (8.4) here. — , Nov 04 '16 at 15:58

score 1 · Answer 1 · answered Nov 04 '16 at 20:15

VHDL has a mechanism to association an alternate name with a named object.

See IEEE Std 1076-2008 6.6 Alias declarations, General 6.6.1 para 1:

An alias declaration declares an alternate name for an existing named entity.

The rules for an object alias are found in 6.6.2 Object aliases. The idea here is to provide a name that can be indexed (8.4 Index names) for the generate statement assignment statement target.

The issue is A0_i is an identifier (15.4) and indivisible lexical element (15.3).

entity fff is
    port (
        a:  in  bit_vector(0 to 3);
        b:  in  bit_vector(0 to 3)
    );
end entity;

architecture sss of fff is
    -- signal A0_0 : bit ;   -- REPLACED
    -- signal A0_1 : bit ;
    -- signal A0_2 : bit ;
    -- signal A0_3 : bit ;
    signal A0:  bit_vector ( 0 to 3);  -- ADDED
-- IEEE Std 1076-2008 6.6 Alias declarations
-- 6.6.1 General
-- An alias declaration declares an alternate name for an existing named entity.
    alias A0_0: bit is A0(0);
    alias A0_1: bit is A0(1);
    alias A0_2: bit is A0(2);
    alias A0_3: bit is A0(3);
begin

U0:  
    for i in 0 to 3 generate
U1:     A0(i) <= a(i) and b(i);
    end generate;

end architecture sss;

Because an object alias can't be created for an unnamed aggregate comprised of named signals the above shows declaring a signal array and the original names aliased to elements of the array.

This modified example with an added entity analyzes and elaborates and will allow use of both an indexed name and an alias name (e.g. A0(0) and A0_0).

generate signal assignmen in vhdl

1 Answers1