Modelsim/Questasim: Unknown entity . Use expanded name

Question

I'm using QuestaSim, which is supposedly the same thing as ModelSim but 64-bit. I'm trying to run a test bench for an assignment due in class tomorrow. The assignment is done and all I need is the test bench, but QuestaSim is being annoying as usual.

For some reason, the test bench file just WILL NOT compile. I cannot for the life of me figure out why, though I recall it working on ModelSim the last time I tried this.

Here's the code for the test bench.

library ieee;
use ieee.std_logic_1164.all;

entity test_bench is
end entity test_bench;

architecture lab1atest of test_bench is
signal  X, Y, M: std_logic_vector (7 downto 0);
signal  s: std_logic;
begin
dut : entity lab1a
port map ( X=>X, Y=>Y, s=>s, M=>M);

stimulus : process is
begin
X <= "10101010"; Y <= "01010101"; s <= '0'; wait for 20 ns;
s <= '1'; wait for 20 ns;
X <= "11110000"; wait for 20 ns;
s <= '0'; wait for 20 ns;
Y <= "00001111";
wait;
end process stimulus;
end architecture lab1atest;

The code for lab1a.vhd I can't post because it's to be submitted for an assignment and I don't want to get nailed for plagiarizing myself, but know that the entity "lab1a" most certainly exists in that file and I am making sure to compile that file first (though I have tried the other way around, just in case).

In addition to the standard selecting of the files and hitting compile, I've also tried the following:

vlib work;
vmap work work;
vcom lab1a.vhd;
vcom lab1atest.vhdl;
vsim work.lab1atest;

Both produce the same error.

If any of you have any idea why I am getting the error highlighted in the title, please let me know. I feel like this is an incredibly simple fix and I am currently cursing the designers of said product for making it so unintuitive.

score 1 · Accepted Answer · 2015-02-03T17:41:09.397

I genned a dummy entity/architecture for lab1a that does nothing but has proper connectivity.

The immediate issue why it won't 'analyze' is that the entity lab1a isn't made visible to test_bench.

dut : entity lab1a
port map ( X=>X, Y=>Y, s=>s, M=>M);

should be

dut: entity work.lab1a
    port map ( ...

or you should make the contents of your working directory visible in your context clause by adding a use clause:

use work.all;  -- or some variant form

After implementing the selected name (work.lab1a, an expanded name is a form of selected name, see IEEE Std 1076-2008, 8.3 Selected names, paragraph 7) the code analyzed with a previously analyzed lab1a:

library ieee;
use ieee.std_logic_1164.all;

entity lab1a is
    port (
        X:  in  std_logic_vector (7 downto 0);
        Y:  in  std_logic_vector (7 downto 0);
        s:  in  std_logic;
        M:  out std_logic_vector (7 downto 0)
    );
end entity;
architecture foo of lab1a is
begin
end architecture;

And why the dummy lab1a works is because an architecture isn't required to contain concurrent statements:

 architecture_body ::=
     architecture identifier of entity_name is
         architecture_declarative_part
     begin
         architecture_statement_part
     end [ architecture ] [ architecture_simple_name ] ;

 architecture_statement_part ::=
      { concurrent_statement }

IEEE Std 1076-2008. 1.3.2 Synaptic description, f):

Braces enclose a repeated item or items on the right-hand side of a production. The items may appear zero or more times; the repetitions occur from left to right as with an equivalent left-recursive rule.

Extended Backus-Naur Form text found in the numbered clauses of the standard is normative.

And there's another solution, the use of a component declaration and component instantiation instead of direct entity instantiation.

This would count on default binding indication to find a previously analyzed lab1a during elaboration. (7.3.3 Default binding indication).

Modelsim/Questasim: Unknown entity . Use expanded name

1 Answers1