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Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

  • Source code editor
  • Compiler
  • Simulator
  • Waveform viewer
  • Interactive debugging such as breakpoints, stepping etc.
  • Signal tracing (dataflow) analysis
  • Code coverage analysis
  • Functional coverage analysis
  • Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions
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VHDL - (modelsim) - Fatal error that indicated during test bench at CASE

I am refreshing my VHDL programming skills (by using ModelSim), I wrote Shift register project and a test bench, I compiled both of them successfully. when I tried to run the TB file, I got a Fatal error that related to CASE: shl(shift…
idan
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ModelSim Fatal error in process RAM_i1/RAM_0_0_0/P107 Lattice MACHXO3L_MISC.vhd

I am facing a fatal error when trying to simulate in ModelSim a design that instantiates a RAM IP for the target device MACHXO3L from Lattice Semiconductor. I have compiled their libraries to use in ModelSim, but the simulations always stop due to…
Edson Manoel
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Exclude some design unit from code coverage on Questasim

I run a code coverage on questasim and I got ucdb file as output. But I need to exclude code coverages of some modules that connect to the top module.I don't need some of modules to be covered which this I can improve coverage report. How can I do…
Buğra Tufan
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Verilog HDL syntax error near "default", expecting "endmodule"

// ProgramCounterTestBench timescale 1ns / 1ps module ProgramCounterTestBench(); logic Clock = 0; logic Reset = 0; logic [15:0] LoadValue; logic LoadEnable; logic signed [8:0] Offset; logic …
Bernardo Silva
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How can i use generic array type with modelsim?

It's my first question here, I really hope you can help me Edit 03 December 2019 : We resolved our problem with the declaration type, but now, we have other problem So, when I tried to run my testbench for the simulation on modelsim, we got these…
Elmatador25
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Error code full_adder.vhd(18): near ")": (vcom-1576) expecting IDENTIFIER

I have this error code full_adder.vhd(18): near ")": (vcom-1576) expecting IDENTIFIER. I have tried the following and the error still occurs, does anyone have an idea? LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE…
Nemer Charbel
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How to display list of Verilog force from Modelsim / Synopsys simulator?

For the ncsim https://community.cadence.com/cadence_technology_forums/f/functional-verification/17382/ncsim-how-to-display-list-of-verilog-force-from-inside-verilog-testbench. How to track the list of Verilog force, is there any simulator/language…
Mana
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VHDL assign a number to signal's name

I am about to use random numbers to choose a signal but can't assign the number to that signal's name. In this code, I have three input ports which their name are: A1B, A2B, A3B, A4B now I want to use them randomly by a rand function between 1 to…
VHDL Verification geek
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How to fix "Unknown formal identifier" error in VHDL

I am facing an error with my VHDL code. I am using ModelSim software for it. I am new in it. There are similar questions posted but that were not solve my problem. Actual issue in port map. I assigned a signals for intermediate wires but it is still…
Ali Raza
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When iam trying to simulate in modelsim there is no obejcts

module alu64bit_test; // Put your code here // ------------------ reg [63:0] a; reg [63:0] b; reg cin; reg [1:0] op; wire [63:0] s; wire cout; // End of your code alu64bit…
Carolina
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Error: (vsim -3389),

I don't understand why I'm getting this error when using model-sim, I've tried a lot of fixes but don't seem to get around this. This is what my modelsim transcript says: ** Error: (vsim-3389) C:/Users/VRN/Desktop/sha256/t_processing.v(31): Port…
vrndandu
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compare modelsim simulation result with a theory text file using vhdl

I would like to compare a modelsim stimuli with a math theory function for that I must export my simulation data from modelsim to .lst file and then create vhdl program who read the .lst file and compare it with math.do file which contain a integer…
Mourad
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Model Sim verilog error Illegal output or inout port connection for port 'out2'

Here is my full code for a 64-bit multiplier. It is giving error at full_multiplier line 17 that I have emboldened (3 stars). The error is vsim-3053 Illegal output or inout port connection for port 'out2'. module full_multiplier(input [63:0] a, b,…
Rizwan Ali
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Errors:TopLevel vhdl on Modelsim

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevel is Port ( reset : in std_logic; clock : in std_logic; coin : in std_logic; push : in std_logic; count1 : out…
Bekbol
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VHDL: Assigning one std_logic_vector to another makes '1' turn to 'X'

I have a baffling problem.. As part of a buffering process I am assigning one std_logic_vector to another, by simply doing: dataRegister <= dataRegisterBuf; The process is synced to a clock. See here for the full process: --! This process buffers…
GrixM
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