An ALU in Verilog, lack of output while simulating

Question

I write an simple ALU in verilog like this:

input [15:0] in;
output reg [15:0] out;

reg [15:0] r [0:7];
reg [3:0] opcode;
reg [3:0] outreg;
reg [3:0] var1, var2;
reg [15:0] a1, a2;

parameter STO = 4'b0000;
parameter ADD = 4'b0001;
parameter MUL = 4'b0010;

always @ (in)
begin

    opcode = in [15:12]; 
    outreg = in [11:8]; 
    var1 = in [7:4];
    var2 = in [3:0];
    a1 = (var1[3]) ? var1[2:0] : r[var1];
    a2 = (var2[3]) ? var2[2:0] : r[var2];
    case (opcode)
        STO: begin r[outreg] = a1; end 
        ADD: begin r[outreg] = a1 + a2; end
        MUL: begin r[outreg] = a1 * a2; end
        SUB: begin r[outreg] = a1 - a2; end
        DIV: begin r[outreg] = a1 / a2; end
        default: begin $display("error input"); end
    endcase
    out = r[outreg];
end

And in test bench, I give such input:

initial begin
$monitor("%d", out);
in = 16'h0280; #10; // STO r2, #0
in = 16'h00d0; #10; // STO r0, #5
in = 16'h01c0; #10; // STO r1, #4
in = 16'h2110; #10; // MUL r1, r1, r0
in = 16'h1221; #10; // ADD r2, r2, r1
end

the result should be (as I predict)

Is that right?

But modelsim shows the answer as follows:

and no output of

ADD r2, r2, r0

Is my prediction of the answer right? Or what's the problem make that happens?

Thanks, I only post key part of my code, SUB/DIV is not used in testing, I forgot delete those two lines, I can handle other problems. After changing `$monitor`, two lines of `20` displayed. But why only one `20` shows with `$monitor("%d", out)` ? — Zh.Z, Sep 23 '16 at 20:27

score 0 · Accepted Answer · answered Sep 23 '16 at 19:44

0

$monitor displays the values of its parameters EVERY time ANY of its parameter changes value. How can you expect two lines of 20?

Ref

answered Sep 23 '16 at 19:44

Thomas B Preusser

1,159
5
10

The only line I see is: `$monitor("%d", out);` – Thomas B Preusser Sep 23 '16 at 19:58
I have 5 lines of inputs `$monitor("%d", out);` dispays only 4 outputs.. But `$monitor("%h, %d", in, out);` can display 5 lines. – Zh.Z Sep 23 '16 at 20:32
Because `out` does NOT change anymore after it is `20`. – Thomas B Preusser Sep 23 '16 at 20:50
so `%h` makes value changes and it can display second `20`. Oh I see. Thank you so much – Zh.Z Sep 23 '16 at 20:51
no, the second 20 line happens because `in` changes – dave_59 Sep 23 '16 at 20:55
The `in` argument is the one changing. `%h` is just its corresponding format specifier. – Thomas B Preusser Sep 23 '16 at 20:55
I added my comment as another answer to get better code formatting – dave_59 Sep 23 '16 at 20:57

score 0 · Answer 2 · answered Sep 23 '16 at 20:53

$monitor("%d", out);

is equivalent to writing this as a separate process.

always @(out)
    $strobe("%d", out); // like $display except prints only once at the end of the time slot

and

   $monitor("%h %d", in,out);

is equivalent to writing this as a separate process.

always @(in or out)
    $strobe("%h %d", in,out); // like $display except prints only once at the end of the time slot

As a general rule, $monitor is only for very simple cases and $display or $strobe should be used instead.

An ALU in Verilog, lack of output while simulating

2 Answers2