Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

Source code editor
Compiler
Simulator
Waveform viewer
Interactive debugging such as breakpoints, stepping etc.
Signal tracing (dataflow) analysis
Code coverage analysis
Functional coverage analysis
Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions

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2 answers

Include files in verilog: compilation options for modelsim

I have to compile a file (x.sv). In x.sv, there are a bunch of "`include y.v". The content of y.v is just a set of assign statements. Ex: assign a = b&&c. Signals a,b and c are defined in x.sv. I tried compiling as follows: vlog -sv -work work…

verilog system-verilog modelsim

asked Sep 28 '17 at 19:06

Benkar

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1 answer

Pulpino ModelSim issue vsim_auto_compile.so 32bit Ubuntu

Hi I have installed Modelsim 32bit version on Ubuntu 16.04. I have also installed relevant 32bit libs and It works fine. (simulation works fine for other projects) However I'm getting this issue when I try to run helloworld at pulpino. make…

ubuntu ubuntu-16.04 32-bit modelsim riscv

asked Aug 28 '17 at 15:16

ashan8k

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0 answers

Is it possible to programmatically define a Hierarchical Name in VHDL 2008?

I have a rather large project, comprised of many modules integrated into one top-level component. I've created test-benches for these modules which make use of API packages (which I've created alongside them). I also have a top-level test-bench that…

vhdl fpga modelsim

asked Jun 21 '17 at 22:10

Alejandro Leal

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0 answers

Instance hierarchy inside VHDL generate block

I have a VHDL code in which I have created several hierarchies inside the generate block, below is the snippet of the code: gen : for i in 1 to WIDTH-1 generate u_4to2 : adder4to2 port map ( op1 => op1(i), op2…

vhdl modelsim

asked Jun 17 '17 at 10:50

sarthak

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1 answer

Modelsim: Does a 'X' in a std_logic_vector affect the other bits in the vector?

I have a Signal myVec : std_logic_vector(8 down 0). Modelsim shows this value: 0X000010. So bit(6) is Undefined. Does this affect other bits for example to bit(1)? I change the state with the following: if myVec(1) = '0' then --change the…

vhdl fpga modelsim quartus

asked Jun 08 '17 at 13:56

dosen

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1 answer

Compiling SystemVerilog DPI with Modelsim DE 10.6b on Ubuntu 64-bit 16.04

I have Modelsim DE 10.6b installed on 64-bit Ubuntu 16.04 and when I run Modelsim examples of SystemVerilog DPI, I get auto compile linking error shown below: ** Fatal: ** Fatal: (vsim-3828) Could not link 'vsim_auto_compile.so': cmd =…

gcc ubuntu-16.04 modelsim system-verilog-dpi

asked Jun 07 '17 at 18:15

seannia

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1 answer

Error Loading Design When using Module inside generate block

I have the following Modules in separate files. When I try the run my RC_ADD_SUB_32 module I get the error Instantiation of 'inst' failed. Region: /RC_ADD_SUB_32_TB/obj/rc_gen_loop[0]/FULL_ADDER The design unit was not found. Error loading Design.…

verilog hdl modelsim

asked May 14 '17 at 05:13

Rager925

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2 answers

Not able write all 32 lines of output in the output file in verilog

I'm trying to write a testbench that will output all the values read and evaluated from a file into a text file. But I can only get a 1 line in the output file instead of the 32 lines. Can someone shed some light? `timescale 100ns/1ps module…

verilog fwrite modelsim

asked Apr 17 '17 at 21:34

JUBER

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3 answers

Modelsim: how to setup 27 MHz clock

I want to setup a 27 MHz clock signal in ModelSim. I usually setup a clock by right clicking that signal -> clock -> setup period. For example, 50 MHz clock -> 20 ns or I used the force statement. Because the 27 MHz clock is special, it is not a…

vhdl modelsim

asked Dec 01 '10 at 16:24

Nissan911

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1 answer

how can I define a combinational user define primitive (UDP) with more than one output?

Is it possible to define a UDP with more than one output? I even try to make bundle output as follow, but it makes some errors. I'm trying to write the code for an 8-bit prefix adder, and I want to define the operation as a UDP to calculate the…

verilog system-verilog modelsim

asked Mar 25 '17 at 12:11

abolfazl taghribi

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1 answer

VUnit: ERROR - Cannot add library named work using `udp_ip_stack-master`

Wanted to try out VUnit, thus followed the Getting Started 1-2-3. For blog 1, I installed Python ver. 3.6 and using ModelSim ver. 10.5a. For blog 2, I downloaded example project udp_ip_stack-master.zip example project, but when I run: python…

vhdl verification xunit modelsim vunit

asked Mar 06 '17 at 15:03

EquipDev

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How to set global simulation folder with generic in VHDL?

I'm trying to give simulation output file folder as a generic for testbench. The testbench would first set the generic to some globally available variable and then different blocks could access this variable to determine the output folder. The…

vhdl modelsim

asked Feb 28 '17 at 08:39

FritzDC

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1 answer

Binding a checker in SystemVerilog

I would like to bind a checker construct to a VHDL module (in QuestaSim) to ensure some verification properties, without having to declare and bind a more (complex) module/interface/agent structure. Without further ado I present you the example code…

bind system-verilog modelsim questasim

asked Feb 21 '17 at 07:16

anthrazithe

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2 answers

Why does this FSM not reach 100% code coverage?

I have the following simple FSM description in VHDL: library ieee; use ieee.std_logic_1164.all; entity coverage1 is port ( clk : in std_logic; rst : in std_logic; req : in std_logic; ack : out std_logic ); end entity…

vhdl code-coverage modelsim questasim

asked Feb 06 '17 at 23:34

Paebbels

15,573
13
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139

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VHDL Booth algorithm

I am trying to implement Booth algorithm in VHDL. I have implemented the ALU, the clock and the shift register so far. Now I want to use these modules to implement the last module which is the actual algorithm, but I do not know how to use these…

algorithm module vhdl shift modelsim

asked Dec 19 '16 at 18:28

didi

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