Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

Source code editor
Compiler
Simulator
Waveform viewer
Interactive debugging such as breakpoints, stepping etc.
Signal tracing (dataflow) analysis
Code coverage analysis
Functional coverage analysis
Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions

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2 answers

Can't compile VHDL package - Modelsim error: (vcom-1576) expecting END

Quite a simple one, but I am pulling my hair out and need some fresh eyes. The problem is detailed below, originally I had the issue with a much larger package containing multiple items so stripped everything back to basics and still can't work it…

asked Oct 11 '18 at 13:23

user7427901

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1 answer

ModelSim Timeline Interval Fix

Today I am working with ModelSim for a lab, and I cannot figure out how to change the timeline interval on the bottom of the screen. I want to have every grey vertical line represent 100 ns, but right now it represents 1000 ns. This is too large for…

modelsim

asked Oct 02 '18 at 14:45

kade

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1 answer

Does anyone know how to use schematic in MODELSIM?

I am unable to use add to schematic in modelsim se64 10.5. Getting this error : Could not open the database because the required debug information has not been generated.

modelsim

asked Aug 15 '18 at 09:10

Mayank

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0 answers

Detecting errors from compilation of vhdl files using vcom

I'm trying to automate the compilation and simulation of a vhdl project in ModelSim. I'm using batch files and using the vcom and vsim commands to compile the VHDL files and simulate the testbenches, respectively. Because it's an automated process…

batch-file modelsim

asked Aug 14 '18 at 08:13

Edlothiad

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1 answer

VHDL Cannot call subprogram "log2" before it is elaborated

I'm using ModelSim PE 10.4a in Windows 10. I'm getting the error below on the code below. I shouldn't be getting this error. It's been a while since I've used modelsim so maybe there is a trick I've forgotten to get it to stop erring erroneously...…

vhdl modelsim

asked Aug 04 '18 at 22:44

user2514676

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1 answer

How to change default color for displaying waves

It seems that recently if you download the intel starter edition of modelsim, the default color of a 1 bit signal on a waveform is barely visible with "extra dark green" color against a black background...even with my laptop brightness cranked to…

modelsim

asked Jul 17 '18 at 19:11

Bimo

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1 answer

Verilog code does not behave as expected

In the following Verilog testbench code i am getting monitor output from time=0 to time=30, but after that i don't get monitor output up to time=70. What is the possible reason for such a behaviour? I am using Modelsim 10.4. //design block for…

verilog simulation hdl modelsim

asked Jul 04 '18 at 14:58

user120908

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1 answer

Value not distributed in time

I have done very simple module where I assign new value on posedge of clock: module block_entry( input logic clk, input entry entry_write, output entry entry_this ); always_ff @(posedge clk) begin entry_this <= entry_write; …

system-verilog modelsim

asked Apr 12 '18 at 17:21

Turbotrdlo

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2 answers

How to generate a detail report of functional coverage in Questasim?

How to generate the detailed coverage report of functional coverage? I am using following command to simulate my code : vlog -64 -work work -vopt +notimingchecks +cover +fcover -f pcie_jammer.f vsim -novopt -c -t ps…


        
            
                
                code-coverage 
                
                modelsim 
                
                questasim 
                
                function-coverage 
                
            
            
                
                    

    asked Apr 12 '18 at 06:16
    
        
    
    
        Himanshu Khandelwal
        
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        How to Instantiate in SystemVerilog
        I am trying to instantiate a module in SystemVerilog.  It compiles in Modelsim with no problems.  When I try to simulate the testbench, it says.
# Loading work.testbench_serial_reader
# ** Error: (vsim-3033)…
        
            
                
                verilog 
                
                system-verilog 
                
                modelsim 
                
            
            
                
                    

    asked Apr 10 '18 at 21:16
    
        
    
    
        Ryu
        
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        With ModelSim, how to obtain all signals' simulation data before adding signals to waveform window?
        Background : ModelSim v10.4d installed with quartus v16.0
I was a Cadence Incisive user, now have to pass to mentor ModelSim, but with ModelSim I can't find a way to get all signals' data before adding them to the waveform window.
For example,
In an…
        
            
                
                vhdl 
                
                verilog 
                
                modelsim 
                
                intel-fpga 
                
            
            
                
                    

    asked Mar 27 '18 at 14:53
    
        
    
    
        Cong Li
        
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        With Modelsim .do file, how to compile a list of files using vcom
        In an Modelsim .do file,
I tried:
vcom file1.vhd file2.vhd

which works fine.
But when I try:
set comp_files "file1.vhd file2.vhd"
vcom $comp_files

it didn't work and I got an error:

Error: (vcom-7) Failed to open design unit file "file1.vhd…
        
            
                
                tcl 
                
                vhdl 
                
                fpga 
                
                modelsim 
                
            
            
                
                    

    asked Mar 26 '18 at 09:54
    
        
    
    
        Cong Li
        
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        Evaluate Assert First when Simulating
        I have an assert in my VHDL code that validates generics passed through the entity of my component. The severity of the assert is set to FAILURE, because I want to quit the simulation if the generics are misused. When simulating with Active-HDL…
        
            
                
                vhdl 
                
                modelsim 
                
            
            
                
                    

    asked Feb 03 '18 at 00:27
    
        
    
    
        ezgoodey
        
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        VHDL 2008 can't drive a signal with an alias of an external name
        Please take a look at the following code, specifically the 3 commented lines at the end. I simulated this with Questasim 10.6c:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity alias_extname_driving_signal is
port(
  clk…
        
            
                
                vhdl 
                
                modelsim 
                
                questasim 
                
            
            
                
                    

    asked Jan 19 '18 at 18:14
    
        
    
    
        Michael Grover
        
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        "after" not working in Modelsim
        I am trying to make a behavorial model of a Serial Adder in Modelsim. 
So, in the design I am trying to pass the Carry_out to the Carry_in after one clock cycle.
The design is: 
one bit, each from two n-bit numbers enter the adder along with the…
        
            
                
                vhdl 
                
                modelsim 
                
            
            
                
                    

    asked Nov 01 '17 at 04:12
    
        
    
    
        Siladittya
        
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