I have to compile a file (x.sv). In x.sv, there are a bunch of "`include y.v". The content of y.v is just a set of assign statements. Ex: assign a = b&&c. Signals a,b and c are defined in x.sv.
I tried compiling as follows: vlog -sv -work work x.sv +incdir+ "path to y.v"
These files have been handed over to me and I have to simulate it.
The reason its done this way is because there are a lot of assign statements in y.v and will make x.sv more readable.
file x.sv
module x (input b, input c, output d);
wire a;
reg d;
`include y.v
always @* d <= a;
endmodule
file: y.v
assign a = b && c;
Modelsim is able to find the files, but it says "near "assign": syntax error, unexpected assign, expecting class." in the file y.v