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I have to compile a file (x.sv). In x.sv, there are a bunch of "`include y.v". The content of y.v is just a set of assign statements. Ex: assign a = b&&c. Signals a,b and c are defined in x.sv.

I tried compiling as follows: vlog -sv -work work x.sv +incdir+ "path to y.v"

These files have been handed over to me and I have to simulate it.

The reason its done this way is because there are a lot of assign statements in y.v and will make x.sv more readable.

file x.sv

module x (input b, input c, output d);
  wire a; 
  reg d;
  `include y.v
  always @* d <= a;
endmodule

file: y.v

assign a = b && c;

Modelsim is able to find the files, but it says "near "assign": syntax error, unexpected assign, expecting class." in the file y.v

Greg
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Benkar
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2 Answers2

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The problem with your code is not because of the `include but with the lines before it. Unfortunately, many syntax errors point to the next line after the error because the mistaken syntax has it lost, and the assign statement in the included file just happens to be the next line.

Your problem is you are mixing two different styles of port declaration syntax; ANSI and non-ANSI style. The reg d; is not expected. Put it into the port header. Other issues after you fix that:

  • Use always_comb and never always @* in SystemVerilog. @* misses events at time 0 as well as constants.
  • Do not use NBAs <= in combinatorial logic.
dave_59
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-1

That should be +incdir+<dir> for each directory you want the simulator to look in for `include'd files. . for the current directory usually works or specify it explicitly.

Brian Magnuson
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  • Modelsim is able to find the files, but it says "near "assign": syntax error, unexpected assign, expecting class." – Benkar Sep 28 '17 at 19:36
  • Ok. You'll have to give us more to work with then. Please include the actual code that is pointed to by the error and preferably a minimal example showing the problem if you can. People are helpful here but not clairvoyant. – Brian Magnuson Sep 28 '17 at 19:41
  • I have added more details. – Benkar Sep 28 '17 at 20:03