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I have a Signal myVec : std_logic_vector(8 down 0). Modelsim shows this value: 0X000010. So bit(6) is Undefined. Does this affect other bits for example to bit(1)?

I change the state with the following:

    if myVec(1) = '0' then
      --change the state to x 
    else
      --change state to y 
    end if;

The problem is that the state always switches to y and I don't know why. Could it be that bit(6) of myVec has an affect to bit(1) or the other bits?

Qiu
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dosen
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  • It's really a bad practice to have undefined states (unless you did it on purpose to meet your requirements). This said, if your condition depends only on a given bit of a vector then it can't depend on the others. – A. Kieffer Jun 08 '17 at 14:04

1 Answers1

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'X' is not undefined. std_logic_1164 defines 'X' as "Forcing Unknown". IF required, 'U' is used for "uninitialized" =~ undefined.

'X' actually means that a signal could not be properly resolved, e.g. it is driven by both '1' and '0'. If you change the type from std_logic to std_ulogic, you will probably see where this happens.

But your question: Unless implemented differently, the individual elements in an array do not affect each other.

JHBonarius
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