Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

Source code editor
Compiler
Simulator
Waveform viewer
Interactive debugging such as breakpoints, stepping etc.
Signal tracing (dataflow) analysis
Code coverage analysis
Functional coverage analysis
Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions

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3 answers

For Verilog/VHDL simulation: how to open modelsim wlf file from command line?

With GtkWave I can simply open a vcd waveform file from the command line as follows: PS> gtkwave waves.vcd Now, I'm needing to switch to modelsim, and need this feature as well. How can I open a modelsim wlf waveform file from the command line and…

vhdl verilog modelsim

asked Jun 06 '19 at 14:13

pico

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1 answer

std_logic_vector (to_unsigned(X, Y));

This is a test-bench, and I have these signals: signal DATA_INPUT :std_logic_vector(0 to 31); signal rand_num :integer; I am trying to put random numbers into this 32bit signal by this: DATA_INPUT <= std_logic_vector(to_unsigned(rand_num,…

vhdl modelsim

asked Apr 24 '19 at 09:20

VHDL Verification geek

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1 answer

modelsim prompt wildcard suggestions/autocomplete disappeared

Normally when I type a command in modelsim, if I have a star * in the command, it lists the available files that match that wildcard. The most common one I do is >do *.do And then a window pops up showing all the files with the extension *.do, and…

modelsim

asked Apr 14 '19 at 00:30

user2913869

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1 answer

modelsim throw error if component is not bound

Is there a way to make modelsim throw an error instead of a warning if a component instance is not bound? Right now, it generates a warning but that is usually hard to spot in the transcript. I don't really have a need to run modelsim if it can't…

modelsim

asked Apr 03 '19 at 14:07

user2913869

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1 answer

SystemVerilog error in multiplexing channels : nonconstant index into instance array

I'm designing a module that accepts multiple channels and outputs one channel. Each channel consists of valid signal and data of some widths. If a channel has valid data, the module should output that channel. If multiple channels have valid data,…

system-verilog modelsim quartus

asked Mar 21 '19 at 12:30

csehydrogen

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1 answer

Ouput of adder module is always don't care [Verilog]

I know VHDL and now I try to do a bit of verilog. I have two files, one that contains a counter and another that contains a 32 bit full adder. Counter.v: module counter ( input clk, input enable, input reset, output reg [3:0] count …

verilog modelsim quartus digital-design

asked Feb 12 '19 at 20:48

sloeberGJ

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1 answer

start from a specific stat in the FSM

I have a specific FSM that works just fine. but I want to start from a specific state in the FSM, I was wondering if I can do it using an event that only happens once in the circuit but I can't do it because all the events I think of keeps the…

vhdl state modelsim fsm quartus

asked Dec 31 '18 at 18:36

islam toukhy

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2 answers

How to implement a test bench file for a 8x1 Multiplexer with 32-bit line width?

I'm writing a VHDL code to model an 8x1 multiplexer where each input has 32-bit width. So I created an array to model the MUX but now I'm stuck with the Test Bench, it's gotten so complicated. Here is my original file (I'm sure it has so many…

vhdl modelsim

asked Dec 20 '18 at 16:26

Daidase

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1 answer

two different errors in modelsim when '=' or '<=' used

I'm learning VHDL, and I've been struggling with this simple example below since yesterday. Write an entity in VHDL for a zero (0) to nine (9) counter, triggered by a positive edge clock and has an asynchronous active high 'reset to zero' input.…

vhdl modelsim

asked Dec 14 '18 at 09:53

Daidase

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1 answer

Error passing type access to function in VHDL

I have a record in VHDL that contains a pointer (access). I need to create a function that receives this record as parameter and from its data write in a file. But simulating with MODELSIM I get the following error: **Error: (vcom-1462) Illegal…

function parameters vhdl modelsim

asked Dec 09 '18 at 16:19

jcc18

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1 answer

ModelSim doesn't recognize the parameter data type?

Here is some Verilog code that I'm trying to run in Modelsim. parameter Data_width = 8; //DATA SIZE input CLK, RST; input [Data _width-1:0] D; When I try to compile it, the compiler complains about Data_width in the last line, saying that it…

verilog modelsim

asked Mar 19 '11 at 01:35

node ninja

31,796
59
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1 answer

Parenthesis error on my assign command for my output (dataflow level)

assign F=((A&B)(~|)(C|D))^((C|D)(~&)((~)A(~|)C)); I have no idea why I get this error: Error: (vlog-13069) C:/Users/JsnK/Desktop/New folder/circuit1_dataflowlvl.v(6): near "(": syntax error, unexpected '('. Here is a schematic :…

verilog modelsim

asked Nov 01 '18 at 19:44

lowspacetop

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1 answer

Modelsim log progress to output file

I'm running Modelsim to do a long simulation. I want to have an ouput like this for my progress report to be logged in a file: Mon Oct 29 21:05:57 IRST 2018 Section 1 Mon Oct 29 21:05:57 IRST 2018 Section 2 Mon Oct 29 21:05:57 IRST 2018 …

tcl modelsim

asked Oct 29 '18 at 17:43

VSB

9,825
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1 answer

Analogue to vlib and vmap in Xilinx Vivado

I have a testing environment that I need to port to Xilinx Vivado. What are the Vivado analogues to Modelsim vlib and vmap ? Please include entire command with any relevant details.

xilinx modelsim vivado

asked Oct 19 '18 at 00:04

Bhawandeep Singh

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1 answer

Modelsim. Length of arrays do not match

I have written a program in modelsim that add to numbers and put the result in Ra/Sum. I have used a tristate buffer, but I get this: Fatal: (vsim-3420) Array lengths do not match. Left is 16 (15 downto 0). Right is 8 (7 downto 0). I understand that…

arrays vhdl simulation modelsim

asked Oct 15 '18 at 21:13

H.Pett

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