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In the following Verilog testbench code i am getting monitor output from time=0 to time=30, but after that i don't get monitor output up to time=70.

What is the possible reason for such a behaviour? I am using Modelsim 10.4.

    //design block for mux
    module mux(output reg out,input[3:0] in,input[1:0] s);

    always @(s or in)

    case(s)

     2'b00:out<=in[0];
     2'b01:out<=in[1];
     2'b10:out<=in[2];
     2'b11:out<=in[3];

    endcase
    endmodule

    //testbench

 module testbench;

    reg[3:0] in;
    reg[1:0] s;
    wire out;

    assign out=0;

    mux m(out,in,s);



    initial
    begin
     s=0;
     in=0;
    $monitor("time=%d , s=%d , in=%d ",$time,s,in);
    while(in<15)
    begin
    while(s<3)
    begin
    s= #10 s+1;
    end
    #40 s<=0;
    #40 in<=in+1;
    end

    end
    endmodule
user120908
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1 Answers1

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The $monitor system task only outputs a line when one of its inputs changes. (excluding the $time etc system functions). Nothing changes between 30ns ad 70ns, hence no lines are output by $monitor.

https://www.edaplayground.com/x/2kQZ

Matthew Taylor
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  • sir, i want to make s=0 at time=40 as well as i want in to be incremented by one too at time=40 , what changes should i make in testbench code – user120908 Jul 04 '18 at 15:13
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    @user120908 Welcome to Stack Overflow. Part of the idea of Stack Overflow is to come up with a set of paired-up questions and answers that will be useful to future Googlers. You asked a question; I answered it. That pair might be useful to someone else in the future. You now have a new question, so please ask it as a new question. Otherwise it will be confusing to future Googlers. – Matthew Taylor Jul 04 '18 at 15:25
  • Take a look at https://stackoverflow.com/questions/32832104/display-vs-strobe-vs-monitor-in-verilog If it doesn't help, ask another question – RaZ Jul 05 '18 at 08:29