Can't compile VHDL package - Modelsim error: (vcom-1576) expecting END

Question

Quite a simple one, but I am pulling my hair out and need some fresh eyes. The problem is detailed below, originally I had the issue with a much larger package containing multiple items so stripped everything back to basics and still can't work it out...

thanks in advance

g

Simple code:

----------------------------------
--  LIBRARY_DECLARATIONS
----------------------------------
library STD;
use     STD.standard.all;
----------------------------------
library IEEE;
use     IEEE.std_logic_1164.all;
----------------------------------
--  PACKAGE_DECLARATION
----------------------------------
package Dummy_pkg is

   component dummy_comp is
      (
         SIG_IN  : in    std_logic;
         SIG_BI  : inout std_logic;
         SIG_OUT : out   std_logic
      );
   end component dummy_comp;

end package TB_PHAS_FPGA_DUT_pkg;

package body TB_PHAS_FPGA_DUT_pkg is
end package body TB_PHAS_FPGA_DUT_pkg;

And this is the error I am getting from Modelsim (MS version):

vcom -reportprogress 300 -work work C:/_WorkDir/pkg_issue/Dummy_pkg.vhd
# Model Technology ModelSim Microsemi vcom 10.5c Compiler 2016.07 Jul 21 2016
# Start time: 13:49:21 on Oct 11,2018
# vcom -reportprogress 300 -work work C:/_WorkDir/pkg_issue/Dummy_pkg.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package Dummy_pkg
# ** Error: C:/_WorkDir/pkg_issue/Dummy_pkg.vhd(20): near "(": (vcom-1576) expecting END.
# End time: 13:49:21 on Oct 11,2018, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0

score 0 · Answer 1 · answered Oct 11 '18 at 13:35

0

You meant:

   component dummy_comp is
      port                           --  <--------------------
      (
         SIG_IN  : in    std_logic;
         SIG_BI  : inout std_logic;
         SIG_OUT : out   std_logic
      );
   end component dummy_comp;

answered Oct 11 '18 at 13:35

Matthew Taylor

13,365
3
17
44

thanks Matt, fresh eyes.. just got it myself - should have refreshed the screen too!!. – user7427901 Oct 11 '18 at 13:46

score 0 · Answer 2 · answered Oct 11 '18 at 13:44

0

Got it - I am missing 'port' from the component declaration.... always after you post... typical... sorry to waste time.
rgds, g.

answered Oct 11 '18 at 13:44

user7427901

11
3

Is there any reason you're putting components in a package? if the source code for dummy_comp is also VHDL, there is no need for a component declaration at all. Since VHDL '93 you can use direct instantiation. This is faster to compile as it compares your instantiation to the entity, rather than to the component and then finding the error later at the mapping stage if the comp doesnt match the entity. Components only really needed when the entity is not written in VHDL. – Tricky Oct 11 '18 at 15:00
@Tricky there are more usecases when a component is needed. At least he is using a package to declare the components instead of copying the code into every architecture that needs the component! – Paebbels Oct 11 '18 at 18:17
@paebbels. Please explain where. If source is VHDL, then unless you're compiling because entity is not yet complete, the only situation where I have needed a component is when source is not VHDL (Verilog, Netlist etc). – Tricky Oct 11 '18 at 22:18
@Tricky explaining this would require more than a comment to this answer and it would be out of scope. Please create a followup questions on StackOverflow or ask me directly on Gitter (same user name). – Paebbels Oct 13 '18 at 23:39
Hiya, I use packages so structural files contain only the instantiation.. This is for testbenching and is part of a large skeleton test harness... I agree with @Tricky, this is a much cleaner method, and much more common - infact, I put just about everything in a package - types, constants procs/fns etc. in this case the components were dummy components used only to drive the outputs on a dummy_dut. When I created the entity I forgot to use the 'port' word so my comparison tool didn't pick it up... to think I've been doing this for over 10 yrs - as I said schoolgirl error!!.. cheers peeps. – user7427901 Oct 15 '18 at 11:17
@Tricky thanks for raising the question: https://stackoverflow.com/questions/52806812/what-is-the-usefulness-of-a-component-declaration - I added the promised use cases for components. – Paebbels Oct 22 '18 at 01:34

Can't compile VHDL package - Modelsim error: (vcom-1576) expecting END

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