First time in VHDL / MODELSIM : can't compile component [(vcom-1576) expecting END.]

Question

I used to come here for C problems and/or Java.

These days I'm learning VHDL and I'm currently stuck in a very small problem. I thought maybe some fresh eyes could give me the solution. I'm that close to get it.

This is a simple 1-BIT ADDER [works fine]

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity ADDC1 is
    port (  A, B, CIN : in std_logic;
            COUT, SUM : out std_logic);

end entity;

architecture DF of ADDC1 is
    begin
        SUM <= A XOR B XOR CIN;
        COUT <= (A AND B) OR (B AND CIN) OR (A AND CIN);


end architecture;

My goal is to make a chained 4-BIT adder with this as a component.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


entity ADDC4 is 
port (
            I1, I2: in std_logic_vector(3 downto 0);
            CIN : in std_logic;
            SUM  : out std_logic_vector(3 downto 0); 
            COUT : out  std_logic );
end entity ADDC4;



architecture STRUCT of ADDC4 is

    component ADDC1(DF) is 
        port (  A: in std_logic; 
                B: in std_logic;
                CIN: in std_logic;
                COUT: out std_logic;
                SUM : out std_logic);
    end component;

    signal COI1,COI2,COI3 : std_logic;

    begin

        AD1:  work.ADCC1 port map (A => I1(0), B => I2(0), CIN => CIN, SUM => SUM(0), COUT => COI1);

        AD2:  work.ADCC1 port map (A => I1(1), B => I2(1), CIN => COI1, SUM => SUM(1), COUT => COI2);

        AD3:  work.ADCC1 port map (A => I1(2), B => I2(2), CIN => COI2, SUM => SUM(2), COUT => COI3);

        AD4:  work.ADCC1 port map (A => I1(3), B => I2(3), CIN => COI3, SUM => SUM(3), COUT => COUT);


end architecture STRUCT;

I checked a few sites, lost an hour, I know it must be a stupid simple thing I'm not seeing because I'm not familiar with the language.

The general idea seems to be good though.

Could you help ?

By the time I have an answer I moved on to a new task also involving a component use. I have the same error and it's the same structure... I hope someone sees the mistake, none of my codes are working. Thanks in advance — Sacha Ketchum, Sep 18 '19 at 18:37

score -1 · Answer 1 · answered Sep 18 '19 at 19:27

A few things were wrong.

Added this at the top

LIBRARY work;

Also, a beginner mistake after a 10hour work day and mud in his eyes

AD1:  work.ADCC1 port map (A => I1(0), B => I2(0), CIN => CIN, SUM => SUM(0), COUT => COI1);

IS WRONG !!!

First : ADDC1 is the correct name !!! (Be careful to your names if you read this looking for a solution)

Second : there's 3 way to write it

AD1:  entity work.ADDC1 port map (A => I1(0), B => I2(0), CIN => CIN, SUM => SUM(0), COUT => COI1);

or

AD1:  entity work.ADDC1(DF) port map (A => I1(0), B => I2(0), CIN => CIN, SUM => SUM(0), COUT => COI1);

or simply

AD1:  ADDC1 port map (A => I1(0), B => I2(0), CIN => CIN, SUM => SUM(0), COUT => COI1);

Last thing : even if my teacher said so...

component ADDC1(DF) is

is an incorrect way to write, you should only do

component ADDC1 is

and then choose one of the above

Hope this post helps someone someday ;)

Cheers to all,

PS : if you wants to save lines in your code, you should do

component ADDC1 is 
        port (  A, B, CIN: in std_logic; 
                COUT, SUM: out std_logic);
    end component;

First time in VHDL / MODELSIM : can't compile component [(vcom-1576) expecting END.]

1 Answers1