How does this SIPO Works?

Question

I am making an UART transceiver, and In that for Receiver section, I need a SIPO to convert the serial data into parallel one, A web search threw out a code which does the required function, I am not able to understand how this particular code works, googling didn't help. I am grateful if someone can point out how this works

library ieee;
use ieee.std_logic_1164.all;

entity RXN_CNTRL is 
  port(
    reset : in std_logic;
    clk : in std_logic;
    din : in std_logic;
    dout : out std_logic_vector(3 downto 0)
  );
end entity;

architecture behave of RXN_CNTRL is 
  signal s : std_logic_vector(3 downto 0) := "0000" ;
begin
  sipo : process (clk, reset)
  begin
    if (reset='1') then
      s <= "0000";
    elsif (rising_edge (clk)) then       
      s <= (din & s(3 downto 1));    
    end if;
  end process;

  dout <= s;

end architecture;

I am not able to understand how the line s <= (din & s(3 downto 1)); works. please clear me in this, I am new to vhdl and want to learn how this works. Thanks

I modified your code so that it actually builds. Hopefully you can see the reason for these edits; It looked like most of the errors were from you trying to reduce a larger entity for the purposes of this question. — scary_jeff, Aug 13 '19 at 09:04
With scary_jeff's changes you can write a [testbench](https://i.stack.imgur.com/hIF9Q.jpg) and [simulate](https://i.stack.imgur.com/9QnQP.jpg) to tell what the assignment statement does. With a little research you could also look up VHDL operators where you'd find the information for the `&` concatenation operator including precedence to avoid extraneous parentheses (e.g. IEEE Std 1076-2008 9.2.5 Adding operators, 9.2.1). — , Aug 13 '19 at 09:34
Thanks @user1155120 , That's enlightening, Will check that out too. — FlyingDodo, Aug 13 '19 at 09:40

score 2 · Accepted Answer · answered Aug 13 '19 at 07:56

In VHDL & is the concatenation operator. It is used to make bigger arrays from smaller arrays and single array elements by concatenating them, ie joining them together. So,

 s <= (din & s(3 downto 1));

takes the single bit din and joins it to the leftmost 3 bits of s (s(3 downto 1)) to give a new value of s:

din  s(3)  s(2)  s(1)

So, you can see that s has been shifted one place to the right and the empty space has been filled with din - exactly the behaviour you'd want for a SIPO.

In VHDL I would recommend always using the combination of concatenation and slicing (taking part of an array, like s(3 downto 1)) for implementing shift-registers and so on. The builtin operators (sla etc) behave in strange ways.

mfro · Answer 2 · 2019-08-13T10:57:38.313

& is the concatenation operator in VHDL.

So what this does is to shift in the newly received bit (din) into s from the left (disposing the lowest bit of s).

Suppose s is "0000" initially. If din = '1', then s <= din & s(3 downto 1) takes din ('1'), concatenates s(3 downto 1)("000") to it and assigns the result to s. The lowest bit of s is 'lost' through this.

I recommend playing through this until you understand what happens.

How does this SIPO Works?

2 Answers2