Output of D flip-flop not as expected

Question

It is async reset. D flipflop when i change reset from one to zero, it doesn't immediately raise the output from zero to one. but when i add in @always ( posedge clk or posedge reset or negedge reset ) it immediately change

Verilog:

module dff_async_reset (
data   , // Data Input
clk    , // Clock Input
reset  , // Reset input
q        // Q output
);
//-----------Input Ports---------------
input data, clk, reset ; 

//-----------Output Ports---------------
output q;

//------------Internal Variables--------
reg q;

//-------------Code Starts Here---------
always @ ( posedge clk or posedge reset)
begin
if (reset) 
  q =0;
else 
  q <= data;
end

endmodule //End Of Module dff_async_reset

Corresponding waveform:

Silicon1602 · Accepted Answer · 2019-08-28T14:39:21.137

It does exactly what you tell it to do: mimic a flip-flop with an asynchronous active-high reset. The following line from your code

always @ (posedge clk or posedge reset)

says: "execute this procedural block when clk makes the transition 0 --> 1 or when reset makes the transition 0 --> 1." In other words, when reset makes the transition 1 --> 0, this always block will not be evaluated.

You value q will only be updated on the positive edge of clk, which is exactly what you want if you want to design a flip-flop.

When you add negedge reset to your sensitivity list, it will indeed immediatelly change when you go out of your reset state (which is 1 --> 0 in your logic). This is, however, usually not desired. Rather, you should synchronize the deassertion of your reset to your clock signal. To quote from the aforementioned website:

The way most of the designs have been modelled needs asynchronous reset assertion and synchronous de-assertion. The requirement of most of the designs these days is:

When reset is asserted, it propagates to all designs; brings them to reset state whether or not clock is toggling; i.e. assertion should be asynchronous

When reset is deasserted, wait for a clock edge, and then, move the system to next state as per the FSM (Finite State Machine); i.e. deassertion should be synchronous

" https://i.stack.imgur.com/1BtDD.png " but in this picture, the deassertion of reset is with clock why the output doesn't go to one despite the clk is one and D is one — Mina Safwat, Aug 28 '19 at 14:54
Ah, I initially missed the picture in your question! The reason for this could be the way you define your clock signal. Please take a look at Gotcha 29 in [Verilog and SystemVerilog Gotchas](https://books.google.be/books?id=_VGghBpoK6cC&lpg=PR12&ots=F2kIzTXUA3&dq=sutherland%20gotcha%2029&hl=en&pg=PA64#v=onepage&q&f=false) by Sutherland & Mills. This chapter describes possible race-conditions that can arise because of clock generation with non-blocking assignments. (Also, usually you should hold your data during a complete clock cycle.) — Silicon1602, Aug 28 '19 at 15:11

score -1 · Answer 2 · answered Jun 28 '22 at 07:31

-1

module PRVO_SLOVO_IMENA(output x,input a,b);

assign x=a&b;

endmodule

module DRUGO_SLOVO_IMENA(output x,input a,b);

assign x=a|b;

endmodule

module TRECE_SLOVO_IMENA(output x,input a,b);

assign x=a^b;

endmodule

module PREZIME(output y, input a,b,c,d);

reg mand,mxor;

TRECE_SLOVO_IMENA o1(.x(mxor),.a(a),.b(b));
PRVO_SLOVO_IMENA o2(.x(mand),.a(mxor),.b(c));
DRUGO_SLOVO_IMENA o3(.x(y),.a(mand),.b(d));

endmodule

answered Jun 28 '22 at 07:31

Jovan Aničić

1

As it’s currently written, your answer is unclear. Please [edit] to add additional details that will help others understand how this addresses the question asked. You can find more information on how to write good answers [in the help center](/help/how-to-answer). – Community Jun 30 '22 at 02:01

score -1 · Answer 3 · answered Jun 28 '22 at 08:19

     module dff(data, clk, reset, q
    );
    input data, clk, reset ; 
    output q;
    reg q;
    
    always @ ( posedge clk)
    if (~reset) begin
    q <= 1'b0;
    end  
    else begin
    q <= data;
    end
    endmodule

    module registar_IME(input clk, reset, [7:0] in, output [7:0] q);
    
    dff dff_1(.data(in[7]), .clk(clk), .reset(reset), .q(q[7]));
    dff dff_2(.data(in[6]), .clk(clk), .reset(reset), .q(q[6]));
    dff dff_3(.data(in[5]), .clk(clk), .reset(reset), .q(q[5]));
    dff dff_4(.data(in[4]), .clk(clk), .reset(reset), .q(q[4]));
    dff dff_5(.data(in[3]), .clk(clk), .reset(reset), .q(q[3]));
    dff dff_6(.data(in[2]), .clk(clk), .reset(reset), .q(q[2]));
    dff dff_7(.data(in[1]), .clk(clk), .reset(reset), .q(q[1]));
    dff dff_8(.data(in[0]), .clk(clk), .reset(reset), .q(q[0]));
    
    endmodule
    
    module registar_PREZIME(input clk, reset, [7:0] in, output [7:0] q);
    
    dff dff_1(.data(in[7]), .clk(clk), .reset(reset), .q(q[7]));
    dff dff_2(.data(in[6]), .clk(clk), .reset(reset), .q(q[6]));
    dff dff_3(.data(in[5]), .clk(clk), .reset(reset), .q(q[5]));
    dff dff_4(.data(in[4]), .clk(clk), .reset(reset), .q(q[4]));
    dff dff_5(.data(in[3]), .clk(clk), .reset(reset), .q(q[3]));
    dff dff_6(.data(in[2]), .clk(clk), .reset(reset), .q(q[2]));
    dff dff_7(.data(in[1]), .clk(clk), .reset(reset), .q(q[1]));
    dff dff_8(.data(in[0]), .clk(clk), .reset(reset), .q(q[0]));
    
    endmodule
        
    module DRUGI_ZADATAK(input clk, reset, [7:0] in, output [7:0] q
        );
    
    
        
    registar_IME r_IME(.clk(clk), .reset(reset), 
     .in(KOPIRAJ_SVOJE_IZ_KOMENTARA), .q(prvi));//OBRISI KAD KOPIRAS poki 
    1'b1011010  vlada 1'b110111  sveta 1'b1000110
    registar_PREZIME r_PREZIME(.clk(clk), .reset(reset), .in(1'b101101), 
    .q(drugi));
    
    endmodule

As it’s currently written, your answer is unclear. Please [edit] to add additional details that will help others understand how this addresses the question asked. You can find more information on how to write good answers [in the help center](/help/how-to-answer). — Community, Jun 28 '22 at 15:48

Output of D flip-flop not as expected

Verilog:

Corresponding waveform:

3 Answers3